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USCMS HCAL Tri. DAS Update Drew Baden University of Maryland http: //www. physics. umd. USCMS HCAL Tri. DAS Update Drew Baden University of Maryland http: //www. physics. umd. edu/hep/HTR/hcal_june_2003. pdf CMS June 2003 1

HTR Status • Rev 1 run Summer 2002 testbeam § Board worked well – HTR Status • Rev 1 run Summer 2002 testbeam § Board worked well – all functional requirements met § Big concern on mechanical issues for production o Had a difficult experience with previous board manufacturing • Rev 2 produced March 2003 § Board production changes: o New assembler, in-house X-ray, DFM review, QC o Gold plated (Rev 1 was white-tin) for better QC § Changes to HTR: o o Change from Virtex 1000 E FBGA (1. 00 mm) to Virtex 2 3000 BGA (1. 27 mm) Added stiffeners Moved all SLB/TPG output to front-panel daughterboards Modified Rx refclk scheme (the usual TTC/refclk clocking concerns) § Full 48 channel capability (Rev 1 was “half HTR”) § As of this date, no issues – this board is functioning well CMS June 2003 2

HTR Rev 3 (cont) Dual-LC O-to-E Stiffeners VME TTC mezzanine Deserializers 6 SLBs Xilinx HTR Rev 3 (cont) Dual-LC O-to-E Stiffeners VME TTC mezzanine Deserializers 6 SLBs Xilinx XC 2 V 3000 -4 CMS June 2003 3

HTR Rev 3 • 30 boards delivered April 21 § Checkout consisted of o HTR Rev 3 • 30 boards delivered April 21 § Checkout consisted of o All systems except connectivity to SLB o Fiber links checked out at 1. 7 Gbaud bit rate (1. 6 Gbaud is CMS requirement) v. Frame clock up to 2. 0 Gbaud bit rate and it stays synchronized v. No BER yet…will do a lab measurement soon v 12 boards x 16 links ~200 links(~5% of total) with no problems v. Used both onboard crystal oscillator and external clock for REFCLK § Minor adjustments will be needed for front panels, stiffeners, etc. § Will battle test these boards this year o May synchronous testbeam just completed o July testbeam o Vertical Slice tests to commence in the fall CMS June 2003 4

Clocks and Synchronization • Clocking considerations can be divided into 2 parts: § Deserializers Clocks and Synchronization • Clocking considerations can be divided into 2 parts: § Deserializers REFCLK: stability critical (80 MHz frame rate) o Stability: must have a very low jitter – 30 to 40 ps pkpk spec o Frequency: TI TLK 2501 spec is 100 ppm (8 k. Hz) to lock v Measured ~350 ppm (30 k. Hz) needed to establish link ØLHC variation expected to be few k. Hz v Once link is established, just needs to be stable (it’s a REFCLK!!!) o Phase: relationship to LHC clock totally irrelevant § Phase critical clock for pipeline synchronization o Must be in phase with LHC clock o Jitter spec is very lose – this clock is used inside FPGA for sequential logic CMS June 2003 5

HCAL Clock Fanout • HTR clocks provided by a single 9 U VME board HCAL Clock Fanout • HTR clocks provided by a single 9 U VME board § Chris Tully/Jeremy Mans from Princeton § Has fiber TTC input • Signals fanned out over Cat 6 twisted pair: § TTC stream o To be used by each HTR and by DCC to decode commands & L 1 A § BC 0 o To be used by SLBs to synchronize TPGs § “ 40 MHz” clock o To be used by FPGA and SLBs to maintain pipeline v Comes from QPLL § “ 80 MHz” clean clock o To be used for deserializer REFCLK v Comes from QPLL CMS June 2003 6

Clock Distribution HTR HTR TTC fiber O/E TTC TTC. . BC 0 TTCrx . Clock Distribution HTR HTR TTC fiber O/E TTC TTC. . BC 0 TTCrx . . FPGA CLK 40 . . . Cat 6 E or Cat 7 Cable . . TTC Brdcst<7: 0>, Brcst. Str, L 1 A BC 0 . . TTCrx CLK 40 distribution to 6 SLBs and to 2 Xilinx QPLL CLK 80 Princeton Fanout Board CMS June 2003 CLK 80 Test Points for. . Rx. CLK and Rx. BC 0 80. 18 MHz to Ref_CLK of SERDES (TLK 2501) 7

TTC receiver - TTCumd • General purpose TTC receiver board (TTCumd) § TTCrx ASIC TTC receiver - TTCumd • General purpose TTC receiver board (TTCumd) § TTCrx ASIC and associated PMC connectors • Will be used to receive TTC signal by HTR, DCC, and clock fanout boards • No signal receivers! § Copper/fiber receivers must be on the motherboard § Signal driven through TTC connectors Princeton Fanout Card • Tested successfully by Maryland, Princeton, BU groups CMS June 2003 8

May Testbeam Setup • Lack of a QPLL or decent equivalent – had to May Testbeam Setup • Lack of a QPLL or decent equivalent – had to improvise: § Front-end used commercial Cypress PLL o Matches GOL 100 ps pkpk jitter spec § Fanout card o No clean 80 MHz REFCLK, so provided 2 alternatives: v 2 x. LHC clock from crystal oscillator v High quality clock from HP signal and pulse generators v Jumper selectable on mezzanine cards o No clean 40 MHz system clock v Just used 40 MHz output from TTCrx chip anyway CMS June 2003 9

May Testbeam Experience • To establish link: § FE o TTC 40 MHz clock May Testbeam Experience • To establish link: § FE o TTC 40 MHz clock cleaned up by Cypress “roboclock” chip (Cy 7 B 993) o FE reset signal to GOL § Fanout card o Fanout from onboard 80. 1576 MHz crystal oscillator for REFCLK o Fanout TTC 40 MHz clock for system clock § HTR o TLK 2501 link circuitry always enabled § Result: Fiber 1. 6 GHz link established ok o No problem locking – worked every time. CMS June 2003 10

Testbeam Experience (cont) • Link stability - VERY PRILIMINARY, STILL STUDYING § Ran 10 Testbeam Experience (cont) • Link stability - VERY PRILIMINARY, STILL STUDYING § Ran 10 hr test on 48 fibers o 3 x 1015 bits o 20% failed to maintain link o During synchronized beam running, sent reset between spills to ensure link § Similar tests at Maryland using TI eval board showed no link errors, similar number of bits sent • Curret plan § Study FE →HTR link at FNAL this month o FNAL test stand setup this week § Investigate noise characteristics of H 2 environment o H 2 is clearly different than FNAL, Maryland BU experience § Review of HTR and Fanout card o Will learn what we need to do from the above • Best guess § All tests in US indicate solid link, but experience in H 2 disagree § Probably some kind of new noise component – figure out and correct. CMS June 2003 11

HCAL TPG • Nothing new since May Electronics Week • TPG under development… § HCAL TPG • Nothing new since May Electronics Week • TPG under development… § Preliminary FPGA code for TPGs done o LUT for linearization (downloadable), 0. 5 Ge. V steps, 255 Gev max ET o E to ET and sums over as many as 7 channels v. Not implemented in code yet…TBD o Muon window in E o BCID filter algorithm TBD from testbeams o Compression LUTs for output to SLBs § Utilization is ~50% of Virtex 2 3000 o We are confident this chip will be sufficient § Simulation effort under way… • Latency issue § See below – we are working on this… CMS June 2003 12

HTR TPG Commissioning • 2 Xilinx FPGAs per HTR § 3 SLBs per Xilinx HTR TPG Commissioning • 2 Xilinx FPGAs per HTR § 3 SLBs per Xilinx § Each mounted on tri. PMC connectors Xilinx • Will test internal connectivity to SLBs R at UMD C T § For signals and for localbus connections • Need a scheme to test HTR/RCT connectivity SLB SLB Xilinx SLB § Not just electrical! Also includes data integrity CMS June 2003 13

HTR/RCT Testing • Will build PMC tester card to mount onto HTR § Host HTR/RCT Testing • Will build PMC tester card to mount onto HTR § Host to 1 or more Wisconsin RCT Vitesse receiver boards Xilinx • Will run the signals from this RCT tester card back into Xilinx § Using 1 HTR, both FPGAs – one source, one sink – to test sending data from HTR to RCT SLB Xilinx RCT • Will try to engineer 3 -SLB test to test single Xilinx → SLB →RCT CMS June 2003 14

HTR Production • Full contingent of HTRs: 260 boards § Includes 10% spares, 20% HTR Production • Full contingent of HTRs: 260 boards § Includes 10% spares, 20% spares for parts • Full production will begin after: § Testbeam demonstrates I/O works under battle conditions § Successful testing of the 6 SLB daughter card functions § Understanding of how to meet latency issues o We are still some clock ticks short, but firmware is still very immature for the TPG part of the HTR (see slides below) • Best guess: fall 2003 § There is no reason to hurry other than to finish with the R&D part of the project § Current board design will be final, perhaps some layout adjustments based on conclusion of testbeam effort CMS June 2003 15

Overall Commissioning Schedule • Summer 2003 testbeam § Repeat previous test w/production prototype boards Overall Commissioning Schedule • Summer 2003 testbeam § Repeat previous test w/production prototype boards • Fall 2003 Slice tests § HCAL will join as schedule allows • 2003/2004 HCAL burn-in § Continue with firmware development/integration as needed • 2004/2005 Vertical Slice and magnet test § We will be ready § All HCAL Tri. Das production cards involved • October 05 beneficial occupancy of USC § Installation of all racks, crates, and cards § We do not anticipate any hardware integration o Should be all firmware / timing / troubleshooting CMS June 2003 16

TPG Latency “Minimizing the trigger latency” • Current total 50 – 57 clocks § TPG Latency “Minimizing the trigger latency” • Current total 50 – 57 clocks § Very rough guesses o Many numbers have not been measured • Optimizations: § § Fiber cables need to be 90 m? HTR firmware needs optimization Deserializer random latency fix TPG cables changed to 15 m will save 1 tick § Others…main efforts over next 6 months CMS June 2003 Item Latency TOF HCAL Optics FE (CCA+QIE) GOL Fiber Tx to HTRs . 5 1 8 -9 2 18 Deserializer HTR Alignment 2 -3 6 HTR TPG path SLB TPG Cables 5 -10 3 4 TOTAL 50 - 57 17

TPG Path TP_Bypass L 1 Filter QIE-data 7 INPUT Lineariz. Sum 10 and Et TPG Path TP_Bypass L 1 Filter QIE-data 7 INPUT Lineariz. Sum 10 and Et Muon LUT 2 Consecutive Time-samples Peak Detection 1 ET[9: 0] 10 Sum 0 in ET Compression ETcomp LUT 8 9 10 Muon bit 1 Mask & Reset Delay to synchronize 2 with BCID 2 2 2 “NO-SHOWER” LUT take care of cases where showers can leak into a cell and incorrectly set the muon bit. BCID avoids to flag as a muon the tail of a more energetic event CMS June 2003 TP 18