Скачать презентацию Universal Asynchronous Receiver Transmitter Dr V Këpuska
093258420e0e803208f3696ae69427ba.ppt
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Universal Asynchronous Receiver Transmitter Dr. V. Këpuska
BF 533 UART Port Controller u Reference: ADSP-BF 533 Blackfin Processor Hardware Reference (doc: BF 5335689413713358021532_hwr. pdf) 3/18/2018 Veton Këpuska 2
BF 533 UART Port Controller u The Universal Asynchronous Receiver/Transmitter (UART) is a n n u The serial communication follows an asynchronous protocol that supports various n n n u full-duplex peripheral compatible with PC-style industry-standard UARTs. The UART converts data between serial and parallel formats. word lengths, stop bits, and parity generation options. The UART includes interrupt handling hardware. Interrupts can be generated from 12 different events. 3/18/2018 Veton Këpuska 3
BF 533 UART Port Controller u The UART is a DMA-capable peripheral with support for separate TX and RX DMA master channels. u It can be used in either n n DMA or programmed non-DMA mode of operation. The non-DMA mode requires software management of the data flow using either interrupts or polling. u The DMA method requires minimal software intervention as the DMA engine itself moves the data. See Chapter 9 of HRM, “Direct Memory Access” for more information on DMA. u Either one of the peripheral timers can be used to provide a hardware assisted autobaud detection mechanism for use with the UART. See Chapter 15 of HRM, “Timers, ” for more information. 3/18/2018 Veton Këpuska 4
Serial Communication u The UART follows an asynchronous serial communication protocol with these options: n n n 5 – 8 data bits 1, 1½, or 2 stop bits None, even, or odd parity Baud rate = SCLK/(16 × Divisor), where SCLK is the system clock frequency and Divisor can be a value ranging from 1 to 65536 u All data words require a start bit and at least one stop bit. With the optional parity bit, this creates a 7 - to 12 -bit range for each word. u The format of received and transmitted character frames is controlled by the Line Control register (UART_LCR). Data is always transmitted and received least significant bit (LSB) first. 3/18/2018 Veton Këpuska 5
Bitstream on the TX Pin 3/18/2018 Veton Këpuska 6
UART Control and Status Registers u u The processor provides a set of PC-style industry-standard control and status registers for each UART. Control and Status Registers are Memory Mapped Registers (MMR). These Memory-Mapped Registers (MMRs) are byte-wide registers (16 -bits) that are mapped as half words with the most significant byte zero filled. n Divisor Latch Registers: (UART_DLH and UART_DLL) n Transmit Holding Register: (UART_THR) n Receive Buffer Register: (UART_RBR) n Interrupt Enable Register: (UART_IER). Consistent with industry-standard interfaces, multiple registers are mapped to the same address location. u The Divisor Latch Access bit (DLAB) in the Line Control Register (UART_LCR) controls which set of registers is accessible at a given time. Software must use 16 -bit word load/store instructions to access these registers. u Transmit and receive channels are both buffered. n The UART_THR register - buffers the Transmit Shift register (TSR) and n The UART_RBR register - buffers the Receive Shift register (RSR). The shift registers are not directly accessible by software. 3/18/2018 Veton Këpuska 7
UART Control and Status Registers: UART Line Control Register u UART_LCR Register n n n 3/18/2018 The UART Line Control Register (UART_LCR) controls the format of received and transmitted character frames. The SB bit functions even when the UART clock is disabled. Since the TX pin normally drives high, it can be used as a flag output pin, if the UART is not used. Veton Këpuska 8
UART Control and Status Registers: Modem Control Register u UART_MCR Register n n 3/18/2018 The Modem Control Register (UART_MCR) controls the UART port, as shown in Figure 13 -3. Even if modem functionality is not supported, the Modem Control register is available in order to support Loopback mode forces the TX pin to high the loopback and disconnects the receiver’s input from mode. the RX pin, but redirects it to the transmit output internally. Veton Këpuska 9
UART Control and Status Registers: UART Line Status Register u UART_LSR Register n 3/18/2018 The UART Line Status Register (UART_LSR) contains UART status information as shown in Figure 13 -4. Veton Këpuska 10
UART Line Status Register u The following bits are cleared when the UART Line Status Register (UART_LSR) is read: n The Break Interrupt (BI), n Overrun Error (OE), n Parity Error (PE) and n Framing Error (FE). u The Data Ready (DR) bit is cleared when the UART Receive Buffer Register (UART_RBR) is read. u Important Note: n Because of the destructive nature of these read operations, special care should be taken. For more information, see “Speculative Load Execution” on page 6 -69 and “Conditional Load Behavior” on page 6 -70. 3/18/2018 Veton Këpuska 11
UART Line Status Register u The THRE bit indicates that the UART transmit channel is ready for new data and software can write to UART_THR. n Writes to UART_THR clear the THRE bit. n It is set again when data is copied from UART_THR to the Transmit Shift register (TSR). u The TEMT bit can be evaluated to determine whether a recently initiated transmit operation has been completed. 3/18/2018 Veton Këpuska 12
UART Control and Status Registers: UART_THR Register u A write to the UART Transmit Holding register (UART_THR) initiates the transmit operation. n 3/18/2018 The data is moved to the internal Transmit Shift Register (TSR) where it is shifted out at a baud rate equal to SCLK/(16 × Divisor) with start, stop, and parity bits appended as required. Veton Këpuska 13
UART_THR Register u All data words begin with a 1 -to-0 -transition start bit. u The transfer of data from UART_THR to the Transmit Shift register (TSR) sets the Transmit Holding Register Empty (THRE) status flag in the UART Line Status register (UART_LSR). u The write-only UART_THR register is mapped to the same address as the read-only UART_RBR and UART_DLL registers. n n n 3/18/2018 To access UART_THR, the DLAB bit in UART_LCR must be cleared. When the DLAB bit is cleared, u writes to this address target the UART_THR register, and u reads from this address return the UART_RBR register. Note data is transmitted and received least significant bit (LSB) first (bit 0) followed by the most significant bits (MSBs). Veton Këpuska 14
UART Control and Status Registers: UART_RBR Register u u u UART_RBR Register The receive operation uses the same data format as the transmit configuration, except that the number of stop bits is always assumed to be 1. After detection of the start bit, the received word is shifted into the Receive Shift Register (RSR) at a baud rate of SCLK/(16 x Divisor). After the appropriate number of bits (including stop bit) is received, the data and any status bits are updated and the Receive Shift Register is transferred to the UART Receive Buffer register (UART_RBR), shown in Figure 13 -6. After the transfer of the received word to the UART_RBR buffer and the appropriate synchronization delay, the Data Ready (DR) status flag is updated. 3/18/2018 Veton Këpuska 15
UART_RBR Register u Sampling Clock Issues: n n u u A sampling clock equal to 16 times the baud rate samples the data as close to the midpoint of the bit as possible. Because the internal sample clock may not exactly match the asynchronous receive data rate, the sampling point drifts from the center of each bit. The sampling point is synchronized again with each start bit, so the error accumulates only over the length of a single word. A receive filter removes spurious pulses of less than two times the sampling clock period. The read-only UART_RBR register is mapped to the same address as the write-only UART_THR and UART_DLL registers. To access UART_RBR, the DLAB bit in UART_LCR must be cleared. n 3/18/2018 When the DLAB bit is cleared, u writes to this address target the UART_THR register, while u reads from this address return the UART_RBR register. Veton Këpuska 16
UART Control and Status Registers: UART_IER Register u u u UART_IER Register The UART Interrupt Enable Register (UART_IER) is used to enable requests for system handling of empty or full states of UART data registers. Unless polling is used as a means of action, the ERBFI and/or ETBEI bits in this register are normally set. 3/18/2018 Veton Këpuska 17
UART_IER Register u Non DMA data transfers u Setting this register without enabling system DMA causes the UART to notify the processor of data inventory state by means of interrupts. n For properation in this mode, system interrupts must be enabled, and appropriate interrupt handling routines must be present. n For backward compatibility, the UART_IIR still reflects the correct interrupt status. u Important Note: The UART features three separate interrupt channels to handle data transmit, data receive, and line status events independently, regardless whether DMA is enabled or not. 3/18/2018 Veton Këpuska 18
UART_IER Register u DMA data transfers u With system DMA enabled, the UART uses DMA to transfer data to or from the processor. Dedicated DMA channels are available to receive and transmit operation. u Line error handling can be configured completely independently from the receive/transmit setup. u The UART_IER register is mapped to the same address as UART_DLH. To access UART_IER, the DLAB bit in UART_LCR must be cleared. 3/18/2018 Veton Këpuska 19
UART_IER Register: DMA u UART’s DMA is enabled by 1. first setting up the system DMA control registers, and then 2. enabling the UART ERBFI and/or ETBEI interrupts in the UART_IER register. u Depending on whether DMA is enabled or not, upon receiving these requests, the DMA control unit either n generates a direct memory access, or n passes the UART interrupt on to the system interrupt handling unit. u However, UART’s error interrupt goes directly to the system interrupt handling unit, bypassing the DMA unit completely. 3/18/2018 Veton Këpuska 20
UART_IER Register: DMA u The ELSI bit enables interrupt generation on an independent interrupt channel when any of the following conditions are raised by the respective bit in the UART Line Status register (UART_LSR): n Receive Overrun Error (OE) n Receive Parity Error (PE) n Receive Framing Error (FE) n Break Interrupt (BI) u When the ETBEI bit is set in the UART_IER register, the UART module immediately issues n an interrupt or n DMA request. u When initiating the transmission of a string, no special handling of the first character is required. n Set the ETBEI bit and let the interrupt service routine load the first character from memory and write it to the UART_THR register in the normal manner. n Accordingly, the ETBEI bit should be cleared if the string transmission has completed. 3/18/2018 Veton Këpuska 21
UART Control and Status Registers: UART_IIR Register u u u UART_IIR Register For legacy reasons, the UART Interrupt Identification register (UART_IIR) still reflects the UART interrupt status. Legacy operation may require bundling all UART interrupt sources to a single interrupt channel and servicing them all by the same software routine. This can be established by globally assigning all UART interrupts to the same interrupt priority, by using the System Interrupt Controller (SIC). When cleared, the Pending Interrupt bit (NINT) signals that an interrupt is pending. The STATUS field indicates the highest priority pending interrupt. n n n The receive line status has the highest priority; the UART_THR empty interrupt has the lowest priority. In the case where both interrupts are signaling, the UART_IIR reads 0 x 06. u When a UART interrupt is pending, the interrupt service routine (ISR) needs to clear the interrupt latch explicitly. The following figure (next slide) shows how to clear any of the three latches. u The TX interrupt request is cleared by n n writing new data to the UART_THR register or by reading the UART_IIR register. n Please note the special role of the UART_IIR register read in the case where the service routine does not want to transmit further data. 3/18/2018 Veton Këpuska 22
UART Control and Status Registers: UART_IIR Register u UART_IIR Register 3/18/2018 Veton Këpuska 23
UART Control and Status Registers: UART_IIR Register u If software stops transmission, it must read the UART_IIR register to reset the interrupt request. n As long as the UART_IIR register reads 0 x 04 or 0 x 06 (indicating that another interrupt of higher priority is pending), the UART_THR empty latch cannot be cleared by reading UART_IIR. u Important Note: n If either the Line Status interrupt or the Receive Data interrupt has been assigned a lower interrupt priority by the SIC, a deadlock condition can occur. To avoid this, always assign the lowest priority of the enabled UART interrupts to the UART_THR empty event. n Because of the destructive nature of these read operations, special care should be taken. For more information, see “Speculative Load Execution” on page 6 -69 and “Conditional Load Behavior” on page 6 -70. 3/18/2018 Veton Këpuska 24
UART Control and Status Registers: UART_DLL and UART_DLH Registers u The bit rate is characterized by the system clock (SCLK) and the 16 -bit Divisor. n The Divisor is split into the UART Divisor Latch Low Byte register (UART_DLL) and n The UART Divisor Latch High Byte register (UART_DLH). n Both registers together form a 16 -bit Divisor. u The baud clock is divided by 16 so that: n BAUD RATE = SCLK/(16 x Divisor) n Divisor = 65, 536 when UART_DLL = UART_DLH = 0 3/18/2018 Veton Këpuska 25
UART_DLL and UART_DLH Registers u u The UART_DLL register is mapped to the same address as the UART_THR and UART_RBR registers. The UART_DLH register is mapped to the same address as the Interrupt Enable register (UART_IER). The DLAB bit in UART_LCR must be set before the UART Divisor Latch registers can be accessed. Important Note: n n 3/18/2018 The 16 -bit Divisor formed by UART_DLH and UART_DLL resets to 0 x 0001, resulting in the highest possible clock frequency by default. If the UART is not used, disabling the UART clock will save power. The UART_DLH and UART_DLL registers can be programmed by software before or after setting the UCEN bit. Veton Këpuska 26
UART_DLL and UART_DLH Registers 3/18/2018 Veton Këpuska 27
UART Control and Status Registers: UART_SCR Register u It is used for generalpurpose data storage and does not control the UART hardware in any way. u The contents of the 8 bit UART Scratch register (UART_SCR) is reset to 0 x 00. 3/18/2018 Veton Këpuska 28
UART Control and Status Registers: UART_GCTL Register u The UART Global Control register (UART_GCTL) contains the enable bit for internal UART clocks and for the Ir. DA (Infra-red Data Association) mode of operation of the UART. 3/18/2018 Veton Këpuska 29
UART_GCTL Register u The Ir. DA TX Polarity Change bit and the Ir. DA RX Polarity Change bit are effective only in Ir. DA mode. u The two force error bits, FPE and FFE, are intended for test purposes. They are useful for debugging software, especially in loopback mode. 3/18/2018 Veton Këpuska 30
DMA Mode of UART u In this mode, separate receive (RX) and transmit (TX) DMA channels move data between the UART and memory. n The software does not have to move data, it just has to set up the appropriate transfers either through u the descriptor mechanism or u through Autobuffer mode. u No additional buffering is provided in the UART DMA channel, so the latency requirements are the same as in non-DMA mode. However, the latency is determined by the bus activity and arbitration mechanism and not by the processor loading and interrupt priorities. u For more information, see Chapter 9, “Direct Memory Access. ” 3/18/2018 Veton Këpuska 31
DMA Mode of UART u DMA interrupt routines must explicitly write 1 s to the corresponding DMA IRQ status registers to clear the latched request of the pending interrupt. u The UART’s DMA is enabled by first setting up the system DMA control registers and then enabling the UART ERBFI and/or ETBEI interrupts in the UART_IER register. n u Depending on whether DMA is enabled or not, upon receiving these requests, the DMA control unit either n n n u This is because the interrupt request lines double as DMA request lines. generates a direct memory access or passes the UART interrupt on to the system interrupt handling unit. However, the UART’s error interrupt goes directly to the system interrupt handling unit, bypassing the DMA unit completely. The UART’s DMA supports 8 -bit operation. 3/18/2018 Veton Këpuska 32
BF 533 Direct Memory Access - DMA BF 533 DMA Support
Processor Memory Architecture • SPORTs, • SPI port, • UART, and • PPI. 3/18/2018 Veton Këpuska 34
BF 533 DMA Support u u The processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the core. DMA transfers can occur between n n u the internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMAcapable peripherals include the u SPORTs, u SPI port, u UART, and u PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. 3/18/2018 Veton Këpuska 35
BF 533 DMA Support u The DMA controller supports both n n one-dimensional (1 D) and two-dimensional (2 D) DMA transfers. u DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. u The 2 D DMA capability supports arbitrary row and column sizes up to 64 K x 64 K elements, and arbitrary row and column step sizes up to +/- 32 K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. 3/18/2018 Veton Këpuska 36
Generic Names of the DMA Memory -Mapped Registers 3/18/2018 Veton Këpuska 37
Analysis of Basic UART Implementation Communication of BF 533 EZ-Kit Lite via RS-232 UART
UART RS-232 3/18/2018 Veton Këpuska 39
UART Transmit Configuration
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 7_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Transmit DMA *p. DMA 7_START_ADDR = tx_buffer; *p. DMA 7_X_COUNT = BUFFER_SIZE; *p. DMA 7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *p. DMA 7_CONFIG = 0 x 1081; 3/18/2018 Veton Këpuska 41
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity with 2 Stop Bits *p. UART_LCR = 0 x 0007; //Enable interrupts for transmit *p. UART_IER = 0 x 0002; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 42
DMA Configuration
DMA Channel’s Peripheral Map Register u Each DMA channel’s Peripheral Map register (DMAx_PERIPHERAL_MAP) contains bits that: n Map the channel to a specific peripheral. n Identify whether the channel is a Peripheral DMA channel or a Memory DMA channel. *p. DMA 7_PERIPHERAL_MAP 3/18/2018 Veton Këpuska = 0 x 7000; 44
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 7_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Transmit DMA *p. DMA 7_START_ADDR = tx_buffer; *p. DMA 7_X_COUNT = BUFFER_SIZE; *p. DMA 7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *p. DMA 7_CONFIG = 0 x 1081; 3/18/2018 Veton Këpuska 45
DMA Configuration Register u The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9 -3 of ADSP-BF 533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes. 3/18/2018 Veton Këpuska 46
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 7_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Transmit DMA *p. DMA 7_START_ADDR = tx_buffer; *p. DMA 7_X_COUNT = BUFFER_SIZE; *p. DMA 7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *p. DMA 7_CONFIG = 0 x 1081; 3/18/2018 Veton Këpuska 47
Transmit_uart_533. c /**************************** This example code tests the UART using the stop mode DMA across two kits. This code is the transmitter code. ****************************/ #include
DMA Start Address Register u The Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR), shown in Figure 9 -2 of ADSP-BF 533 Blackfin Processor Hardware Reference, also in the next slide, contains the start address of the data buffer currently targeted for DMA. 3/18/2018 Veton Këpuska 49
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 7_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Transmit DMA *p. DMA 7_START_ADDR = tx_buffer; *p. DMA 7_X_COUNT = BUFFER_SIZE; *p. DMA 7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *p. DMA 7_CONFIG = 0 x 1081; 3/18/2018 Veton Këpuska 50
DMA Count Register u For 1 D DMA, it specifies the number of elements to read in. For 2 D DMA details, see “Two-Dimensional DMA” on page 9 -45 of ADSP-BF 533 Blackfin Processor Hardware Reference. A value of 0 in X_COUNT corresponds to 65, 536 elements. 3/18/2018 Veton Këpuska 51
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 7_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Transmit DMA *p. DMA 7_START_ADDR = tx_buffer; *p. DMA 7_X_COUNT = BUFFER_SIZE; *p. DMA 7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *p. DMA 7_CONFIG = 0 x 1081; 3/18/2018 Veton Këpuska 52
DMAx Modify Register u u The Inner Loop Address Increment register (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, two’scomplement byte-address increment. In 1 D DMA, this increment is the stride that is applied after transferring each element. Note X_MODIFY is specified in bytes, regardless of the DMA transfer size. 3/18/2018 Veton Këpuska 53
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 7_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Transmit DMA *p. DMA 7_START_ADDR = tx_buffer; *p. DMA 7_X_COUNT = BUFFER_SIZE; *p. DMA 7_X_MODIFY = 1; // Autobuffer DMA Continously transmit the data *p. DMA 7_CONFIG = 0 x 1081; 3/18/2018 Veton Këpuska 54
DMA Configuration Register u The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9 -3 of ADSP-BF 533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes. *p. DMA 7_CONFIG = 0 x 1081 3/18/2018 Veton Këpuska 55
UART Port Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity with 2 Stop Bits *p. UART_LCR = 0 x 0007; //Enable interrupts for transmit *p. UART_IER = 0 x 0002; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 56
UART Line Control Register *p. UART_LCR = 0 x 0080 3/18/2018 Veton Këpuska 57
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity with 2 Stop Bits *p. UART_LCR = 0 x 0007; //Enable interrupts for transmit *p. UART_IER = 0 x 0002; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 58
UART Divisor Latch Low Byte Register u Divisor = 0 x 000001 FF = 255 *p. UART_DLL = 0 x 01 FF *p. UART_DLH = 0 x 0000 3/18/2018 Veton Këpuska 59
Boud-Rate u BAUD RATE = SCLK/(16 x Divisor) n SCLK/(16 x 255) = SCLK/4096 n SCLK = 100 MHz n BAUD RATE = 100 MHz /4096 = 24414. 0625 bps 3/18/2018 Veton Këpuska 60
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity with 2 Stop Bits *p. UART_LCR = 0 x 0007; //Enable interrupts for transmit *p. UART_IER = 0 x 0002; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 61
UART Line Control Register u Resetting UART_LRC Register *p. UART_LRC = 0 x 0000 3/18/2018 Veton Këpuska 62
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity with 2 Stop Bits *p. UART_LCR = 0 x 0007; //Enable interrupts for transmit *p. UART_IER = 0 x 0002; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 63
UART Line Control Register u Setting UART_LRC Register *p. UART_LRC = 0 x 0007 3/18/2018 Veton Këpuska 64
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity with 2 Stop Bits *p. UART_LCR = 0 x 0007; //Enable interrupts for transmit *p. UART_IER = 0 x 0002; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 65
UART_IER Interrupt Enable Register *p. UART_IER = 0 x 0002 3/18/2018 Veton Këpuska 66
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity with 2 Stop Bits *p. UART_LCR = 0 x 0007; //Enable interrupts for transmit *p. UART_IER = 0 x 0002; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 67
UART_GCTL UART Global Control Register *p. UART_GCTL = 0 x 0001 3/18/2018 Veton Këpuska 68
UART Receive Configuration
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 6_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Receive DMA *p. DMA 6_START_ADDR = rx_buffer; *p. DMA 6_X_COUNT = BUFFER_SIZE; *p. DMA 6_X_MODIFY = 1; *p. DMA 6_CONFIG = 0 x 0083; 3/18/2018 Veton Këpuska 70
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity *p. UART_LCR = 0 x 0003; //Enable interrupts for receive *p. UART_IER = 0 x 0001; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 71
DMA Configuration
DMA Channel’s Peripheral Map Register u Each DMA channel’s Peripheral Map register (DMAx_PERIPHERAL_MAP) contains bits that: n Map the channel to a specific peripheral. n Identify whether the channel is a Peripheral DMA channel or a Memory DMA channel. *p. DMA 7_PERIPHERAL_MAP 3/18/2018 Veton Këpuska = 0 x 6000; 73
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 6_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Receive DMA *p. DMA 6_START_ADDR = rx_buffer; *p. DMA 6_X_COUNT = BUFFER_SIZE; *p. DMA 6_X_MODIFY = 1; *p. DMA 6_CONFIG = 0 x 0083; 3/18/2018 Veton Këpuska 74
DMA Configuration Register u The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9 -3 of ADSP-BF 533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes. 3/18/2018 Veton Këpuska 75
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 6_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Receive DMA *p. DMA 6_START_ADDR = rx_buffer; *p. DMA 6_X_COUNT = BUFFER_SIZE; *p. DMA 6_X_MODIFY = 1; *p. DMA 6_CONFIG = 0 x 0083; 3/18/2018 Veton Këpuska 76
Receive_uart_533. c /**************************** This example code tests the UART using the stop mode DMA across two kits. This code is the receiver code. ****************************/ #include
DMA Start Address Register u The Start Address register (DMAx_START_ADDR/MDMA_yy_START_ADDR), shown in Figure 9 -2 of ADSP-BF 533 Blackfin Processor Hardware Reference, also in the next slide, contains the start address of the data buffer currently targeted for DMA. 3/18/2018 Veton Këpuska 78
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 6_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Receive DMA *p. DMA 6_START_ADDR = rx_buffer; *p. DMA 6_X_COUNT = BUFFER_SIZE; *p. DMA 6_X_MODIFY = 1; *p. DMA 6_CONFIG = 0 x 0083; 3/18/2018 Veton Këpuska 79
DMA Count Register u For 1 D DMA, it specifies the number of elements to read in. For 2 D DMA details, see “Two-Dimensional DMA” on page 9 -45 of ADSP-BF 533 Blackfin Processor Hardware Reference. A value of 0 in X_COUNT corresponds to 65, 536 elements. 3/18/2018 Veton Këpuska 80
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 6_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Receive DMA *p. DMA 6_START_ADDR = rx_buffer; *p. DMA 6_X_COUNT = BUFFER_SIZE; *p. DMA 6_X_MODIFY = 1; *p. DMA 6_CONFIG = 0 x 0083; 3/18/2018 Veton Këpuska 81
DMAx Modify Register u u The Inner Loop Address Increment register (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) contains a signed, two’scomplement byte-address increment. In 1 D DMA, this increment is the stride that is applied after transferring each element. Note X_MODIFY is specified in bytes, regardless of the DMA transfer size. 3/18/2018 Veton Këpuska 82
UART Configuration in DMA Mode /**************************** Function to configure the UART & DMA ****************************/ void setup_UART() { // Clear the DMA configuration register *p. DMA 6_CONFIG = 0 x 0; // Configure the UART DMA parameter registers // Receive DMA *p. DMA 6_START_ADDR = rx_buffer; *p. DMA 6_X_COUNT = BUFFER_SIZE; *p. DMA 6_X_MODIFY = 1; *p. DMA 6_CONFIG = 0 x 0083; 3/18/2018 Veton Këpuska 83
DMA Configuration Register u The DMA Configuration register (DMAx_CONFIG/MDMA_yy_CONFIG), shown in Figure 9 -3 of ADSP-BF 533 Blackfin Processor Hardware Reference, also in this slide is used to set up DMA parameters and operating modes. *p. DMA 7_CONFIG = 0 x 0083 3/18/2018 Veton Këpuska 84
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity *p. UART_LCR = 0 x 0003; //Enable interrupts for receive *p. UART_IER = 0 x 0001; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 85
UART Line Control Register *p. UART_LCR = 0 x 0080 3/18/2018 Veton Këpuska 86
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity *p. UART_LCR = 0 x 0003; //Enable interrupts for receive *p. UART_IER = 0 x 0001; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 87
UART Divisor Latch Low Byte Register u Divisor = 0 x 000001 FF = 255 *p. UART_DLL = 0 x 01 FF *p. UART_DLH = 0 x 0000 3/18/2018 Veton Këpuska 88
Boud-Rate u BAUD RATE = SCLK/(16 x Divisor) n SCLK/(16 x 255) = SCLK/4096 n SCLK = 100 MHz n BAUD RATE = 100 MHz /4096 = 24414. 0625 bps 3/18/2018 Veton Këpuska 89
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity *p. UART_LCR = 0 x 0003; //Enable interrupts for receive *p. UART_IER = 0 x 0001; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 90
UART Line Control Register u Resetting UART_LRC Register *p. UART_LRC = 0 x 0000 3/18/2018 Veton Këpuska 91
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity *p. UART_LCR = 0 x 0007; //Enable interrupts for receive *p. UART_IER = 0 x 0001; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 92
UART Line Control Register u Setting UART_LRC Register *p. UART_LRC = 0 x 0008 3/18/2018 Veton Këpuska 93
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity *p. UART_LCR = 0 x 0003; //Enable interrupts for receive *p. UART_IER = 0 x 0001; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 94
UART_IER Interrupt Enable Register *p. UART_IER = 0 x 0001 3/18/2018 Veton Këpuska 95
UART Control Registers Configuration // Configure the UART Control Registers // Enable the divisor latch access *p. UART_LCR = 0 x 0080; *p. UART_DLH = 0 x 0000; *p. UART_DLL = 0 x 01 FF; // disable the divisor latch access *p. UART_LCR = 0 x 0000; //Enable 8 -bit mode without parity *p. UART_LCR = 0 x 0003; //Enable interrupts for receive *p. UART_IER = 0 x 0001; // UART Clock Enabled *p. UART_GCTL = UCEN; } 3/18/2018 Veton Këpuska 96
UART_GCTL UART Global Control Register *p. UART_GCTL = 0 x 0001 3/18/2018 Veton Këpuska 97
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