Triggering on Particle Types: Calorimeter and Muon Based Triggers Sridhara Dasu Department of Physics University of Wisconsin-Madison Many slides stolen from: Sergio Cittolin, James Linnemann, and Wesley Smith http: //www. hep. wisc. edu/~dasu/public/Dasu. IEEETrg. pdf IEEE NSS & MIC, Norfolk, Virginia, November 2002 1
Contents 1. Calorimeter Triggers 1. Electrons, Photons, t-leptons and Jets 2. Global energy triggers 3. Energy clustering algorithms We will discuss the 2. Muon Triggers 1. Pattern matching 2. Minimum ionizing signal 3. Electrons and Muons triggers by examples that I am familiar with and in the process bring out the general themes. 1. Track Matching 4. Specific implementation examples 1. e+e- (Ba. Bar) 2. e-p (ZEUS) and Fixed target () 3. p-pbar (CDF, D 0, ATLAS, CMS) 5. Technologies: ASICs, FPGAs, . . . 6. Future IEEE NSS & MIC, Norfolk, Virginia, November 2002 2
e+-e- B Physics: Ba. Bar, Belle Purpose of the trigger is to pass most (if not all) collision events Discriminate against beamenvironment collisions Hardware trigger (L 1) 2 Level Trigger • Tracks + Energy • < 2. 5 k. Hz Software trigger (L 3) • ~ 100 Hz to tape • Remove background • Prescale Bhabhas IEEE NSS & MIC, Norfolk, Virginia, November 2002 Type Rate (Hz) Physics 180 Cosmic 100 Random 20 Beam Background 1000 -2000 3
Ba. Bar L 1 Trigger Overview 1. Calorimeter Trigger 1. N-bit pattern of energy deposits in crystals 2. Tagged by f angle 3. Total f-map from 10 TPBs 4. Used in combination with the track trigger 2. Muon Trigger 1. 3 -bit pattern representing hit topology in the muon chambers (RPCs) 2. Used for cosmic trigger 3. Drift Chamber Trigger 1. Track stubs 2. PT discrimination 3. Main trigger for Ba. Bar IEEE NSS & MIC, Norfolk, Virginia, November 2002 4
ZEUS QCD Physics Trigger on Electrons Jets, Missing ET Total ET IEEE NSS & MIC, Norfolk, Virginia, November 2002 5
Note: Divide by 100 for CDF, D 0 Hadron Collider Experiments: CDF, D 0, ATLAS, CMS IEEE NSS & MIC, Norfolk, Virginia, November 2002 B Physics (10 Ge. V) • 2 -5 Ge. V particles • 10 k. Hz (Tevatron) • Specific Channels, Tracks + Separated vertices • 1 MHz (LHC) - Hopeless for ATLAS, CMS Physics at EWSB scale (250 Ge. V) • 115 < Mhiggs < 200 Ge. V • Couplings to W (80), Z (91) • Lepton PT ~ 40 Ge. V • Te. V scale supersymmetry • Multiple leptons, jets and LSPs (missing PT), PT < 100 Ge. V QCD Background • Jet ET ~ 250 Ge. V Rate = 1 k. Hz (LHC), 0. 01 Hz (Tevatron) • Jet fluctuations electron BG • Decays of p, k, B muon BG Technical challenges • 7, 40 MHz input fast processing • 100 Hz output physics selection 6
Hadron Collider L 1 Trigger Challenge CDF, D 0 ZEUS ATLAS, CMS Bunch crossing (ns) 132 (396) 96 25 Decision latency (ms) 4 5 2, 3 2000 8000 2525 to 7, 50 100 to 0. 5 40000 to 100 Channel count Rate reduction (k. Hz) Short timescales Large channel count Large rate reduction IEEE NSS & MIC, Norfolk, Virginia, November 2002 1. Faster, high density 2. electronics with 3. fancy algorithms 7
Overview : ZEUS Pipelined 3 level trigger Level-1 (Electronics) Calorimeter Trackers Level-2 (Processors) Calorimeter Trackers Level-3 (Software) Event Reconstruction IEEE NSS & MIC, Norfolk, Virginia, November 2002 8
Overview : CDF Trigger IEEE NSS & MIC, Norfolk, Virginia, November 2002 9
Overview : D 0 Trigger 7 MHz input rate Data Framework L 1/Lum 4. 2 ms 7 k. Hz 128 terms IEEE NSS & MIC, Norfolk, Virginia, November 2002 Data Log L 2 L 3 100 ms 1000 Hz 48+ ms 50 Hz 128 terms 48 nodes 10
Overview : D 0 Framework IEEE NSS & MIC, Norfolk, Virginia, November 2002 11
Overview : ATLAS & CMS Examples ATLAS CMS IEEE NSS & MIC, Norfolk, Virginia, November 2002 12
ATLAS and CMS Strategy Complexity handled in software on CPUs IEEE NSS & MIC, Norfolk, Virginia, November 2002 13
Theme Level-1: Energy over threshold (Ba. Bar, Belle, CDF, D 0) to object identification (ZEUS, CDF, D 0) to object isolation (ATLAS, CMS) Level-2: Custom processors (CDF, D 0, ZEUS) to full readout after Level-1 (Ba. Bar, CMS) We will talk only about Level-1 Calorimeter and Muon triggers More sophisticated algorithms possible at level-2, separated vertices for B physics, etc. are discussed in other talks. IEEE NSS & MIC, Norfolk, Virginia, November 2002 14
Interaction of Particles with Matter IEEE NSS & MIC, Norfolk, Virginia, November 2002 15
Projective Geometry Projective geometry is important • ZEUS: Used complicated cable mapping and pattern searches to reduce fake rate • ATLAS, CMS: Calorimeters are built projective • Mapping with muon system: Important for isolation IEEE NSS & MIC, Norfolk, Virginia, November 2002 16
D 0 Muon System h IEEE NSS & MIC, Norfolk, Virginia, November 2002 17
D 0 Calorimeter Trigger IEEE NSS & MIC, Norfolk, Virginia, November 2002 18
D 0 Calorimeter Trigger IEEE NSS & MIC, Norfolk, Virginia, November 2002 19
D 0 Muon Trigger IEEE NSS & MIC, Norfolk, Virginia, November 2002 20
D 0 Muon Trigger IEEE NSS & MIC, Norfolk, Virginia, November 2002 21
D 0 Muon Trigger IEEE NSS & MIC, Norfolk, Virginia, November 2002 22
ZEUS Calorimeter Trigger Electronics 16 Crates Trigger Encoder Cards, Adder Cards Identify and count objects over threshold Electrons, Jets Energy sums Geometry VME Crate Custom P 2 & P 3 bus ECL logic runs at 2 x, i. e. , 20 MHz, on TEC, Adder IEEE NSS & MIC, Norfolk, Virginia, November 2002 23
ZEUS Trigger Encoder Card Analog input from calorimeter • Digitize Flash ADC EMC, HAC • Characterize • Sum Bussed backplane for transferring data to Adder Cards Discrete ECL Logic IEEE NSS & MIC, Norfolk, Virginia, November 2002 24
ZEUS Adder Card Object identification using pattern of energy deposition in the calorimeter. IEEE NSS & MIC, Norfolk, Virginia, November 2002 25
CDF, D 0 Level 2 CDF and D 0 elected for simple level-1 but more sophisticated level-2 based on processors IEEE NSS & MIC, Norfolk, Virginia, November 2002 26
Level-2 Crate IEEE NSS & MIC, Norfolk, Virginia, November 2002 27
Level-2 Crate IEEE NSS & MIC, Norfolk, Virginia, November 2002 28
Level-2 Data Bus IEEE NSS & MIC, Norfolk, Virginia, November 2002 29
Level-2 Software IEEE NSS & MIC, Norfolk, Virginia, November 2002 30
D 0 Use of Generic L 2 Processors IEEE NSS & MIC, Norfolk, Virginia, November 2002 31
D 0 L 2 Trigger : Calorimeter Objects IEEE NSS & MIC, Norfolk, Virginia, November 2002 32
D 0 Level-2 Electron IEEE NSS & MIC, Norfolk, Virginia, November 2002 33
D 0 Level-2 Muon IEEE NSS & MIC, Norfolk, Virginia, November 2002 34
D 0 Level-2 Global Trigger IEEE NSS & MIC, Norfolk, Virginia, November 2002 35
Calorimeter Geometry : CMS Example EB, EE, HB, HE map to 18 RCT crates Provide e/g and jet, t, ET triggers IEEE NSS & MIC, Norfolk, Virginia, November 2002 36
Trigger Mapping: CMS Example IEEE NSS & MIC, Norfolk, Virginia, November 2002 37
CMS ECAL Front-end Electronics IEEE NSS & MIC, Norfolk, Virginia, November 2002 38
ECAL Front-end Boards Serves one trigger tower 5 x 5 crystals Trigger Primitives: BCID, Energy, FG IEEE NSS & MIC, Norfolk, Virginia, November 2002 39
ECAL Frontend ASICs One ASIC but two personalities Final Algorithms in ASICs (0. 25 m Rad. Hard) Prototypes using FPGAs Gigabit optical to surface Trigger Primitives DAQ IEEE NSS & MIC, Norfolk, Virginia, November 2002 ET sum for trigger tower 1 -bit characterizing fine-grain energy deposit profile (FG) Different chips but similar output for HCAL 40
Synchronization IEEE NSS & MIC, Norfolk, Virginia, November 2002 41
CMS Electron/Photon Algorithm Limit region of interest to minimum possible IEEE NSS & MIC, Norfolk, Virginia, November 2002 42
t / Jet Algorithm Reduce amount of data at each level to minimum needed IEEE NSS & MIC, Norfolk, Virginia, November 2002 43
Missing / Total ET Algorithm 360 o Strip ET sum over all h Ey 18 Df = 20 o used instead of HCAL tower size: Df = 5 o E T 2 E T 1 40 o 20 o 0 o -5 LUT Ex 18 For sums ET scale LSB (quantization) ~ 1 Ge. V is used …… f ET 18 0 h IEEE NSS & MIC, Norfolk, Virginia, November 2002 5 ET E x 2 2 1 Ey Ex E y 1 MET 44
CMS Tower Level Memory LUT 8 -bit nonlinear EM ET 1 -bit EM fine-grain bit 8 -bit nonlinear HD ET Lookup table for arbitrary nonlinear transform - including making E+H and H/E 7 -bit linear ET 1 -bit H/E, FG Veto Electron 9 -bit linear ET 1 -bit Activity Jet / t Fully programmable LUT, Current default values: - Electron scale: 0. 5 Ge. V LSB, Emax=63. 5 Ge. V - Veto: OR of fine-grain veto and H / E < 5% - Jet / t scale (E+H): 1. 0 Ge. V LSB, Emax=511 Ge. V - Jet energy (12 x 12 tower sum), Emax=1 Te. V - Activity level for t pattern: E > 2 Ge. V, H > 4 Ge. V IEEE NSS & MIC, Norfolk, Virginia, November 2002 45
CMS Calorimeter Trigger Crate Data from calorimeter FE on Cu links @ 1. 2 Gbaud • Into 126* rear Receiver Cards • Prototype tested w/ ASICs Backplane links fix the algorithm 160 MHz point to point backplane (prototype tested) Spares • 18 Clock&Control (prototype tested), 126 Electron ID (prototype tested), not 18 Jet/Summary Cards -- all cards operate @ 160 MHz included* • Use 5 Custom Gate-Array 160 MHz Ga. As Vitesse Digital ASICs • Phase, Adder, Boundary Scan, Electron Isolation, Sort (manufactured) IEEE NSS & MIC, Norfolk, Virginia, November 2002 46
CMS Regional Calorimeter Trigger Prototypes Clock delay adjust DC-DC Converters IEEE NSS & MIC, Norfolk, Virginia, November 2002 Clock and Control Card Fans out 160 MHz clock & adjusts phase to all boards 47
4 x 1. 2 GB/s Copper Links 20 m 22 AWG Copper Cable, VGA Connector Receiver mezzanine card Results: Bit Error rate < 10 -15 Test Transmit mezzanine card IEEE NSS & MIC, Norfolk, Virginia, November 2002 Serial Link Test Cards 48
Crate & Backplane VME 48 V externally supplied Std. Custom VME Point-to-point Slots Dataflow Front Custom Point-to-point Dataflow VME Power Supply Rear 160 MHz with 0. 4 Tbit/sec dataflow • Initial tests indicate good signal quality Designed to incorporate algorithm changes • New Non-Isolated Electron, Tau & Jet Triggers Many data paths checked manually and with JTAG • Note: we only have one RC and one EIDC for testing • Plan: one complete fully tested crate for slice test IEEE NSS & MIC, Norfolk, Virginia, November 2002 49
CMS Receiver Card Full featured final prototype board is in test - ASIC testing successful. Continue to test all data paths - develop software etc. - FY 2003 program • Phase ASIC validated, BSCAN ASIC validated - all RC ASIC procurement now complete Adder PHASE ASICs mezz link cards BSCAN ASICs MLUs DC-DC Top side with 1 of 8 mezzanine cards & 2 of 3 Adder ASICs IEEE NSS & MIC, Norfolk, Virginia, November 2002 Bottom side with all Phase & Boundary Scan ASICs 50
CMS RCT : Adder ASIC Key RCT technology Fast ASICs - compact design IEEE NSS & MIC, Norfolk, Virginia, November 2002 51
CMS Electron Isolation Card Full featured final prototype board is finished & under test. • Electron ID & Sort ASICs tested by Vitesse before delivery • In house testing fully validated SORT ASIC & mostly validated EISO ASIC neighbor data requires multiple cards. • SORT ASIC procurement complete • Detailed tests of all data paths: FY 2003 EISO SORT ASICs EISO IEEE NSS & MIC, Norfolk, Virginia, November 2002 52
Jet-Summary Card Being Assembled • Electron/photon/muon info. • SORT ASICs to find top four electron/photons • Threshold for muon bits • To GCT • Region energies • To cluster crate • Absorbs HF functionality • Reuses Receiver Mezzanine Card • To cluster crate IEEE NSS & MIC, Norfolk, Virginia, November 2002 53
CMS Global Calorimeter Trigger 1 GB/s serial inter-crate 3 GB/s serial backplane Cable backplane for flexibility IEEE NSS & MIC, Norfolk, Virginia, November 2002 54
CMS Global Calorimeter Trigger Generic: Common CMS, ATLAS IEEE NSS & MIC, Norfolk, Virginia, November 2002 55
CMS Muon Detectors IEEE NSS & MIC, Norfolk, Virginia, November 2002 56
CMS Muon Overview ASICs FPGAs ASIC to FPGAs FPGA IEEE NSS & MIC, Norfolk, Virginia, November 2002 57
CMS Muon Trigger Primitives Memory to store patterns Fast logic for matching FPGAs are ideal IEEE NSS & MIC, Norfolk, Virginia, November 2002 58
CMS Muon Trigger Track Finder Memory to store patterns Fast logic for matching FPGAs are ideal Sort based on PT, Quality - keep loc. Combine at next level - match Sort again - Isolate? Match with RPC Improve efficiency and quality IEEE NSS & MIC, Norfolk, Virginia, November 2002 Top 4 highest PT and quality muons with location coord. 59
CMS Global Trigger IEEE NSS & MIC, Norfolk, Virginia, November 2002 60
Trigger Flow : ATLAS Example IEEE NSS & MIC, Norfolk, Virginia, November 2002 61
ATLAS Calorimeter Algorithms I IEEE NSS & MIC, Norfolk, Virginia, November 2002 62
ATLAS Calorimeter Algorithms II IEEE NSS & MIC, Norfolk, Virginia, November 2002 63
Calorimeter Trigger Overview : ATLAS Trigger Primitives • Analog sum Receiver • Quality cable plant Preprocessor • ADC, Bunch-crossing • LUT, sums Algorithm Implementation • Jets, SET, Missing ET • e/g, t/h FPGA Based Generic Processors (adopted for CMS GCT) IEEE NSS & MIC, Norfolk, Virginia, November 2002 64
ATLAS Muon Trigger Detectors IEEE NSS & MIC, Norfolk, Virginia, November 2002 65
ATLAS Muon Trigger IEEE NSS & MIC, Norfolk, Virginia, November 2002 66
ATLAS Trigger Central Processor IEEE NSS & MIC, Norfolk, Virginia, November 2002 67
CMS Calorimeter Trigger Rates: 2 x 1033 cm-2 s-1 Mock Trigger Table Selected Scenario: 5 k. Hz e/g, 5 k. Hz t, jets, 1 k. Hz combined, rest m IEEE NSS & MIC, Norfolk, Virginia, November 2002 68
CMS Calorimeter Physics Efficiency: 2 x 1033 cm-2 s-1 Scenario: 5 k. Hz e/g, 5 k. Hz t, jets, 1 k. Hz comb, rest m No generator level cuts other than requiring trigger objects within calo. (h<5) or tracker (e, g, t) acceptance IEEE NSS & MIC, Norfolk, Virginia, November 2002 69
Improving L 1 Efficiency for qq. H SUSY higgs production in weak boson fusion • Accompanied by jets in the forward direction Forward jet characteristics • Lower jet ET, but potential beam background Strategy at level-1 • Trigger on higgs decay products • Decays to Z (ee, mm) or photons • Low threshold electron/photon algorithm • Decays to t • • Narrow jet tag - developed better algorithm (2000) Tag jets with location information • Invisible decays (c) • Missing ET trigger by itself is not efficient • Require two tag jets also • Require Dh between the jets • Decays to b jets (dominant but dirty mode) • Four jet trigger including forward tag jets • Require Dh between jets • Exploit that central b jets must be back-to-back IEEE NSS & MIC, Norfolk, Virginia, November 2002 70
Global L 1 Trigger Algorithms IEEE NSS & MIC, Norfolk, Virginia, November 2002 71
qq. H to 2 b-jets + 2 tag jets 2 p b q 1 -5 q 2 b -2. 5 0 2. 5 5 Current Level-1 Trigger • 4 jets anywhere in the detector Exploit separation of the tag jets in h • 4 jets with Dh > 3 • Reduce 1 -jet rate to compensate for new rate Rate reduction using event topology cuts • Rapidity gap due to lack of color connection • Require b-jets to be within the central detector Algorithm 1, 2, 3, 4 jet triggers only Additional Dh>3 cut IEEE NSS & MIC, Norfolk, Virginia, November 2002 Efficiency for MH=110 Ge. V Efficiency for MH=130 Ge. V 70% 76% 79% (+9%) 82% (+8%) 72
High Level Trigger Strategy IEEE NSS & MIC, Norfolk, Virginia, November 2002 73
Evolution of Level-1 Triggers Input Old - separate analog trigger sums + Cu cables New - on detector ADCs++ (radiation hard ASICs) trigger primitives formation, giga-bit fiber-optic transport Backplanes Old - VME Bus, Fast. Bus New - Point-to-point high speed links, serial (1 to 3 GB/s) or parallel (160 MHz) Inter-crate links Old - Parallel differential ECL New - Serial 1. 2 GB fiber or Cu links IEEE NSS & MIC, Norfolk, Virginia, November 2002 74
Evolution of Level-1 Triggers Discrete Logic D 0, CDF towers over thresholds + sums ZEUS sums + pattern logic for object ID ASICs CMS RCT object identification isolation, sorting, fast adders FPGAs Almost everywhere Generic processors IEEE NSS & MIC, Norfolk, Virginia, November 2002 75
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