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TMA 1271 - Introduction to Machine Architecture n Reference Book: ¨ n n Ramesh TMA 1271 - Introduction to Machine Architecture n Reference Book: ¨ n n Ramesh S. Goankar, “Microprocessor Architecture, Programming and Applications with 8085”, 5 th Edition, Prentice Hall Week 1 – Microprocessor Basic Concepts & 8085 Micrprocessor Architecture Week 2 – Addressing Modes & Classifications of Instructions of 8085 Week 3 & 4 – Instruction Set of 8085 Microprocessor Week 5 – Study of 8255 Programmable Peripheral Interface

TMA 1271 - Introduction to Machine Architecture n n n n Week 6 – TMA 1271 - Introduction to Machine Architecture n n n n Week 6 – Programming Exercise I Week 7 – Programming Exercise II Week 8 – Programming Exercise III Week 9 – Programming Exercise IV Week 10 – Programming Exercise V Week 11 – Programming Exercise VI Week 12 – Lab Test (Batch A) Week 13 – Lab Test (Batch B)

n Assessment scheme: ¨ Programming Exercises – 12% (2% n Result & Experimentation – n Assessment scheme: ¨ Programming Exercises – 12% (2% n Result & Experimentation – 10 marks n Report – 10 marks n Total = 20 marks/10 – 2% ¨ Lab Test – 8 % n Flowchart – 20 marks n Program – 40 marks n Result – 20 marks n Total = 80 marks/10 – 8% each)

Organization of A Microprocessor-based System (Computer) n n CPU – Central Processing Unit Memory Organization of A Microprocessor-based System (Computer) n n CPU – Central Processing Unit Memory ¨ ¨ n I/O ¨ ¨ n n ROM – Read Only Memory RAM – Random Access Memory Keyboard Display Device Clock – Square Wave Oscillator (Timing) System Bus

n Microprocessor (CPU) ¨ Programmable integrated device (silicon chip) that has computing & decision n Microprocessor (CPU) ¨ Programmable integrated device (silicon chip) that has computing & decision making capabilities ¨ Communicates & operates in binary numbers 0 & 1, called bits ¨ Has a fixed set of instructions in the form of binary patterns – machine language ¨ Difficult for humans to remember machine language – each instruction is represented using abbreviated names (mnemonics)

n Memory ¨ Symbolic representation Word length 1 word instruction 2 word instruction n n Memory ¨ Symbolic representation Word length 1 word instruction 2 word instruction n n address n Word: no. of bits micro-P recognizes and processes at a time ( 4 - 64 bit ). Instruction: combination of bit patterns with specific meaning known to micro-P. Program: Set of all instructions.

n I/O ¨ Microprocessor’s connection to the outside world Input: Keyboard, mouse n Output: n I/O ¨ Microprocessor’s connection to the outside world Input: Keyboard, mouse n Output: Monitor, printer n

n System Bus – wires connecting memory & I/O to microprocessor ¨ Address n n System Bus – wires connecting memory & I/O to microprocessor ¨ Address n n Unidirectional Identifying peripheral or memory location ¨ Data n n Bus Bidirectional Transferring data ¨ Control n n n Bus Synchronization signals Timing signals Control signal

n Actions performed by microprocessor: ¨ CPU – Memory ¨ CPU – I/O ¨ n Actions performed by microprocessor: ¨ CPU – Memory ¨ CPU – I/O ¨ Data Processing n n Arithmetic operations Logical operations ¨ Control n n Jump Interrupts

Basic Concepts of Microprocessors n Differences between: Microcomputer – a computer with a microprocessor Basic Concepts of Microprocessors n Differences between: Microcomputer – a computer with a microprocessor as its CPU. Includes memory, I/O etc. ¨ Microprocessor – silicon chip which includes ALU, register circuits & control circuits ¨ Microcontroller – silicon chip which includes microprocessor, memory & I/O in a single package. ¨

n Differences between: High level language ¨ Assembly language ¨ Machine language ¨ n Differences between: High level language ¨ Assembly language ¨ Machine language ¨

Architecture of Intel 8085 Microprocessor Architecture of Intel 8085 Microprocessor

Intel 8085 Microprocessor n Microprocessor consists of: ¨ Control unit: control microprocessor operations. ¨ Intel 8085 Microprocessor n Microprocessor consists of: ¨ Control unit: control microprocessor operations. ¨ ALU: performs data processing function. ¨ Registers: provide storage internal to CPU. ¨ Interrupts ¨ Internal data bus

n Registers ¨ General Purpose Registers n B, C, D, E, H & L n Registers ¨ General Purpose Registers n B, C, D, E, H & L (8 bit registers) n Can be used singly n Or can be used as 16 bit register pairs ¨ n BC, DE, HL H & L can be used as a data pointer (holds memory address) ¨ Special Purpose Registers n Accumulator (8 bit register) Store 8 bit data ¨ Store the result of an operation ¨ Store 8 bit data during I/O transfer ¨

n Flag Register 8 bit register – shows the status of the microprocessor before/after n Flag Register 8 bit register – shows the status of the microprocessor before/after an operation ¨ S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity flag) & CY (carry flag) ¨ D 7 ¨ D 6 D 5 D 4 D 3 D 2 D 1 D 0 S Z X AC X P X CY Sign Flag n n n Used for indicating the sign of the data in the accumulator The sign flag is set if negative (1 – negative) The sign flag is reset if positive (0 – positive)

n Zero Flag Is set if result obtained after an operation is 0 ¨ n Zero Flag Is set if result obtained after an operation is 0 ¨ Is set following an increment or decrement operation of that register ¨ 10110011 + 01001101 -------1 0000 n Carry Flag ¨ Is set if there is a carry or borrow from arithmetic operation 1011 0101 + 0110 1100 -------Carry 1 0010 0001 1011 0101 - 1100 -------Borrow 1 1110 1001

n Auxillary Carry Flag ¨ Is set if there is a carry out of n Auxillary Carry Flag ¨ Is set if there is a carry out of bit 3 1011 0101 + 0110 1100 -------1 0010 0001 n Parity Flag Is set if parity is even ¨ Is cleared if parity is odd ¨

n 16 – Bit Registers ¨ Program n n n A pointer to the n 16 – Bit Registers ¨ Program n n n A pointer to the next instruction to be executed Contains the 16 -bit memory address of the next instruction Updated after processor has fetched the instruction ¨ Stack n n n Counter Pointer Stack – an area in memory in which temporary info is stored Stack – FILO (First In Last Out) basis Holds the address of the top of the stack

Non Programmable Registers n Instruction Register & Decoder Instruction is stored in IR after Non Programmable Registers n Instruction Register & Decoder Instruction is stored in IR after fetched by processor ¨ Decoder decodes instruction in IR ¨ Internal Clock generator 3. 125 MHz internally ¨ 6. 25 MHz externally ¨

Basic Working of a Microprocessor n n Instructions are stored sequentially in memory Microprocessor Basic Working of a Microprocessor n n Instructions are stored sequentially in memory Microprocessor Fetches instruction from memory ¨ Decodes instruction ¨ Executes instruction ¨

Interrupts of 8085 Microprocessor n Maskable Interrupts ¨ Microprocessor can ignore or delay interrupt Interrupts of 8085 Microprocessor n Maskable Interrupts ¨ Microprocessor can ignore or delay interrupt request n n n INTR – General purpose interrupt RST 5. 5, RST 6. 5, RST 7. 5 – Restart interrupts, higher priorities Nonmaskable Interrupts Enabled by default ¨ Cannot be disabled ¨ Microprocessor must respond to it immediately ¨ n TRAP – highest priority

Grouping of Signals of 8085 Microprocessor n n n Power supply and frequency signals Grouping of Signals of 8085 Microprocessor n n n Power supply and frequency signals Address bus signals Data bus signals Control and status signals Externally initiated signals & external signal acknowledgement Serial I/O port signals

Address bus signals, Data bus signals n AD 0 -AD 7, A 8 -A Address bus signals, Data bus signals n AD 0 -AD 7, A 8 -A 15 ¨ 16 address lines – 2 sets ¨ Most significant bits (A 8 -A 15) – single directional ¨ Least significant bits (AD 0 -AD 7) – bidirectional n n Multiplexed with the bits of bi-directional data bus It is used as both address and data bus

Control and status signals n Status lines: _ ¨ IO/M n n n ¨ Control and status signals n Status lines: _ ¨ IO/M n n n ¨ n Differentiate I/O and memory applications High – I/O Low – Memory S 1, S 0 – status signals, to indicate the type of machine cycle in progress Control _ lines: __ _ ¨ RD, WR & INTA n n n RD – data on the data bus to be read into processor WR – data on the data bus to be written to processor INTA – acknowledge an INTR interrupt

Externally initiated signals & signal acknowledgement n Initiated signals Reset In – reset CPU Externally initiated signals & signal acknowledgement n Initiated signals Reset In – reset CPU ¨ Hold – suspend CPU operation ¨ Ready – CPU go into wait state, to sync with slower devices ¨ n Signal acknowledgement Reset out – high once CPU is rest ¨ HLDA – acknowledges hold signal ¨