TLA 7000 Series Logic Analyzer Breakthrough solutions for real-time digital systems analysis Product Fact Sheet The speed you need, the visibility you want, the flexibility you desire Features Magni. Vu™ acquisition i. Capture™ multiplexing Benefits Avoid missing events completely in either timing or state acquisition mode with higher sampling resolution (up to 20 ps) on all channels Eliminate double probing with simultaneous digital and analog acquisition through a single logic analyzer probe i. View™ display Gain complete system visibility with time-correlated, integrated analog and digital data on one display i. Verify™ analysis Quickly find signal integrity issues with multi-channel bus analysis using oscilloscope-generated eye diagram Automated measurements Easily summarize your design’s performance with sophisticated measurements such as: frequency, period, pulse width, duty cycle, and edge count Drag & drop triggers Quickly isolate events through simple and intuitive trigger setup. Triggers include: Channel Edge, Channel Value, Bus Value, Multi-Group Value, Glitch, Setup and Hold Violation, or Trigger on Anything Performance you can see Featuring: § Modular mainframes provide flexibility and expandability, from 2 -slot TLA 7012 and 6 -slot TLA 7016 § All measurement modules are fully interchangeable between TLA 7012 and TLA 7016 § 68/102/136 channel modules with up to 128 Mb record length § Up to 20 ps (50 GHz) high-speed timing resolution § Up to 156 ps (6. 4 GHz)/128 Mb deep memory timing analysis § Up to 1. 4 GHz / 3. 0 Gb/s state acquisition analysis § Control and monitor the TLA Series remotely over the network § PCI Express Gen 1 through Gen 3 Including Gen 3 Protocol to Physical Layer Analysis for Link Widths from x 1 through x 16
TLA 7000 Series Logic Analyzer Key specifications and ordering information Modules TLA 7 SAxx Channels/Lanes Record Length State Clock Rate (per module) (Qtr/Half/Full CH) 4, 8 lanes Up to 16 GB (x 16) Up to 8 GT/s (2 modules for x 16) (160 MSym/Lane) Product Fact Sheet Timing (Qtr/Half/Full CH) (Magni. Vu™ acquisition) -- -- TLA 7 ACx 68, 102, 136 ch 235 MHz std; 450 MHz opt. 8/4/2 Mb to 512/256/128 Mb 500 ps / 1 ns / 2 ns 125 ps TLA 7 BBx 68, 102, 136 ch 750 MHz std; 1. 4 GHz opt. --/4/2 Mb to --/128/64 Mb 156. 25 ps / 312. 5 ps / 625 to 50 ns 20 ps Recommended Probes and Accessories Key Options Key Applications § Signal integrity TLA 7012 Portable mainframe; 2 modules; built-in 15 inch (38. 1 cm) display PG 3 AMOD Digital pattern generator module Opt. 18 Optional touch screen A wide variety of probes are recommended, including: Opt. 1 C Add i. View™ external oscilloscope interface kit P 67 SAxx 08 or 16 -Differential Inputs (x 4 or x 8) PCI Express midbus Opt. 1 K Add LACART logic analyzer cart P 67 SA 16 G 2 Opt. R 3/R 5 3 or 5 year repair service plan 16 -Differential Inputs PCI Express Gen 2 midbus Opt. C 3/C 5 3 or 5 year calibration service plan P 67 SAxx. S 08 or 16 -Differential Inputs PCI Express slot interposer P 67 SA 01 SD 1 -channel PCI Express solder-down 34 -channel general-purpose Benefits Magni. Vu™ acquisition’s high speed timing resolution of up to 20 ps § Memory § Easily measure signals inside Altera or Xilinx FPGA designs and select which group of internal signals to probe without having to recompile TLA 7016 Benchtop mainframe; 6 modules; requires external computer P 6860 34 -channel high-density Opt. 1 C Add i. View™ external oscilloscope interface kit P 6960 34 -channel single-ended high-density with DMax® probing technology Opt. 1 K Add LACART logic analyzer cart P 6962 Opt. R 5 5 year repair service plan Opt. C 3/C 5 3 or 5 year calibration service plan 34 -channel (optimized for half channel mode) single-ended high-density with D-Max® probing technology P 6964 34 -channel (optimized for qtr channel mode) single-ended high-density with D-Max® probing technology § Serial data § Analyze from the protocol to the physical layer for PCI Express Gen 1 through Gen 3 with up to 8. 0 GT/s acquisition rates and up to 16 GB deep memory (for x 16 Link) § MIPI 34 -channel differential high-density with DMax® probing technology Copyright © 2011 Tektronix All rights reserved. § Perform complete validation of digital timing performance for the latest speeds of DDR 3 and GDDR § FPGA P 6810 P 6980 § Find elusive glitches and events with 2/11 JS/WWW 54 W-21074 -5 § Verify protocol and analyze proprietary versions of the Dig. RF standard without specialized external hardware
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