TLA 6000 Series Logic Analyzer Fact Sheet Breakthrough solutions for real-time digital systems analysis Features A Comprehensive Signal Integrity Toolset at an Unprecedented price Benefits Comprehensive Signal Integrity Debug Toolkit with: Glitch Trigger, Capture and Display Quickly find signal integrity problems by triggering on common problems such as crosstalk and termination errors. Exclusive glitch display removes need to manually search all channels by showing both the time and channel where any signal integrity problems occurred i. Capture™ multiplexing Eliminate double probing and see both digital and analog acquisitions through a single logic analyzer probe i. View™ display Gain complete system visibility with time-correlated, integrated analog and digital data on one display Performance and Ease to debug digital systems Magni. Vu™ acquisition Accurately determine signal relationships with high sampling resolution (125 ps) on all channels Automated measurements Easily summarize your design’s performance with sophisticated measurements such as: frequency, period, pulse width, duty cycle, and edge count Drag & drop triggers Quickly isolate events through simple and intuitive trigger setup. Triggers include: Channel Edge, Channel Value, Bus Value, Multi-Group Value, Glitch, Setup and Hold Violation, or Trigger on Anything Featuring: § i. Capture™ eliminates messy double probing of signals § i. View™ time-correlated digital-analog view to clearly see how analog anomalies affect your digital signals § Up to 450 MHz state acquisition provides analysis of high-speed synchronous digital circuits § 500 ps (2 GHz) with 128 Mb timing record length to capture intermittent events over a wide time window § 125 ps-resolution Magni. Vu™ acquisition simultaneous with timing or state acquisition to find elusive timing problems quickly, without double probing § Automated drag-and-drop measurements ensure faster setup and analysis for common tasks § Drag-and-drop triggers simplify the task of isolating problems and data of interest
TLA 6000 Series Logic Analyzer Fact Sheet Key specifications and ordering information Models Channels State Clock Rate (per module) Record Length (Full CH) Timing (Qtr/Half/Full CH) Timing (Magni. Vu™ acquisition) TLA 6202 68 235 MHz (std) 450 MHz (opt) 2 Mb (std), 8 Mb, 32 Mb, 500 ps / 1 ns / 2 ns 128 Mb 125 ps TLA 6203 102 235 MHz (std) 450 MHz (opt) 2 Mb (std), 8 Mb, 32 Mb, 500 ps / 1 ns / 2 ns 128 Mb 125 ps TLA 6204 136 235 MHz (std) 450 MHz (opt) 2 Mb (std), 8 Mb, 32 Mb, 500 ps / 1 ns / 2 ns 128 Mb 125 ps Key Options Recommended Accessories Key Applications Must choose one of the following probe options PG 3 L Digital pattern generator in a separate chassis § FPGA Opt. 1 P Add full complement of P 6810 34 channel general-purpose probes LACART Accessory Cart 650 -4815 -xx Opt. 2 P Add full complement of mictor probes Additional Removable Hard Drive Assembly (No SW) 196 -3494 -xx Flying Leadset for P 6960 Probe 196 -3472 -xx 8 -Ch Differential Leadset for P 6810 Opt. 3 P Add full complement of P 6960 34 channel DMAX probes Opt. 18 Add Touchscreen Opt. 1 C Enable Full Analog Multiplexer Opt. R 5 complex designs: physical layer, timing, bus transactions and software execution. Increase to 450 MHz State Speed Opt. AM § View complete operation of today’s Bus Debug and Verification Increase to 128 Mb base record length per channel Opt. 45 § Processor and Increase to 32 Mb base record length per channel Opt. 3 S or Xilinx FPGA designs and select which group of internal signals to probe without having to recompile Increase to 8 Mb base record length per channel Opt. 2 S § Easily measure signals inside Altera Add i. View™ external oscilloscope interface kit Opt. 1 S Benefits 5 year repair service plan § Signal integrity § Find elusive glitches and events with Magni. Vu™ acquisition’s high speed timing resolution of up to 20 ps © 2011 Tektronix 52 W-25757 -2 2/11 JS/WOW
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