Thermal Limitations and Solutions for Microelectronic Systems Driven

Thermal Limitations and Solutions for Microelectronic Systems Driven by the Economics of Moore’s Law Paul J. Boudreaux Consultant & Senior Scientist University Research Foundation Laboratory for Physical Sciences College Park, MD 20740 boudreau@eng. umd. edu Tel: 301 -935 -6547 April 4, 2005 UMBC Presentation

What does the future portend for high performance microelectronic systems for thermal & power distribution? 93 W/cm 2 40 W/cm 2 68 W/cm 2 Think the shuttle has a thermal management problem? Consider the next generation of high performance chips: >160 Watts/cm 2

State-of-the-Art Thermosyphon in Commercial Work Stations • 100 Watt - 6 pipe finned tower • 30 cubic inches • 30 fins per stack • 100 -150 ft 3/min air flow required • Cools only 1 chip (1 cm 2 )

Modern Impediments to Chip Design • Thermal Limitations < 90 o. C Qjc • Current Density: JAl < 4 x 105 Amps/cm 2 • Material Breakdown Potential, Emax= Vmax/dmin Emax (typical) = 1 Volt/10 nanometers = 100 x 106 V/m • Power Density < 250 Watts/cm 2 • Random Soft Errors in Logic & Analog Circuits – Signals are a countable number of electrons ~ < 105 electrons – Thermal noise fluctuations – Quantum noise: particle decay, cosmic rays, radiation induced SEU

Consider a Mixed Analog/Digital/MEMs System’s In-Plane Thermal Gradients • d. T/dt , DT and CTE are major problems • Analog voltages are temperature sensitive • In-situ stress/strain causes failure thru DT Potential Solutions: Heat spreaders with high K values attached to the chip can help alleviate lateral DT problems. Placing the system or components into a forced isothermal environment also reduces DT, d. T/dt and CTE related problems. Severing thermomechanical heat path reduces or eliminates shock and vibration from entering the system while reducing weight.

Moore’s Law Shannon-von Neumann. Landauer (SNL) Switching Energy Per Bit* Ebit>ESNL= k. BT ln 2 = 0. 017 e. V @300 K Using the Uncertainty Relations for x & t, one calculates the max integration density of binary switches ~ 5 x 1013 devices/cm 2, Power Dissipation per unit Area ~ 4 x 106 W/cm 2 ! We are at a Thermal Management Barrier (TMB) long before we get to the limits from Moore’s law or the semiconductor laws of physics! * ”Limits to Binary Logic Switch Scaling – A Gedanken Model”, Zhirnov, et al, Proc. of IEEE, Vol. 91, No. 11, Nov 2003, pp 1934 -1938.

Spray Cooling: One Possible Answer A Phase Change Methodology to Heat Removal that is Isothermal While Also Severing the Thermomechanical Heat Path

Phase Change: Spray Cooling System Can Meet These Requirements But It Requires An Active Cooling System Vapor Return Heat Rejection Condenser/ Heat Exchanger Low power density, low DT heat rejection Pump Filter Fan Delivery and Return Tubes (Can be Part of Chassis Frame with Quick-Disconnects) Heat Acquisition Spray Cooling Cap Cooled MCM or IC Package Electronic Circuit Board Liquid Out Compact Pump-Condenser Unit Typically Mounted at Rear of Enclosure or Externally Heat can be acquired at high power density levels, enabling circuitry to be compacted to very small board areas, while heat is rejected remotely, where providing larger condenser (radiator) areas and airflow is not a problem.

Isothermal Spray Cooling Directly Onto the Chip Surface Pressurized Liquid from Pump Enters Spray Manifold Liquid Inlet Spray Nozzles Create Fine Cooling Mist Impinging on IC Chips 20 -30 psi Typical Vapor and Excess Spray Drawn Out Suction Tube for Return to Condenser Suction Outlet 1 atm (Not Pressurized) Typical IC Die (Shown Flip-Chip Mounted with Underfill) MCM Substrate (Illustrated with Integral BGA Package) Printed Circuit Board

400 Watt Ceramic Package/ MCM with Spray Cooled Lid 400 W MCM Spray Nozzle Array Vapor Out Fluid In Top View w/Underside of Lid Side View w/Lid Attached

Phase Change: Spray Cooling Attributes • • • Used for point-of-source cooling or system wide cooling Demonstrated > 150 W/cm 2 heat extraction Forces Isothermal surface conditions wherever phase change occurs Severs thermomechanical heat path enabling vibration and shock isolation Direct heat removal from the IC chip surface for minimum Qj Conformable to surfaces, small liquid volumes required Phase change fluids enable the choice of operating conditions over a large temperature range (77 K-380 K) Active cooling requires a “dead man’s hand” system to remove trapped heat within the system when power fails Capable of reliable zero-g operation, gives additional cosmic ray protection from SEU due to electrostatic charge buildup in spacecraft Mechanical pump reliability can be 99. 999999% with redundancy Phase change fluids require chemical and mechanical filters for long term reliability; fluids must be chemically stable, environmentally friendly Will not meet $0. 10/Watt commercial costs in present form

Consider the Materials Used for the Thermal Conductivity Part of the Problem Assumptions: • Simple thermal conductivity model P=dq/dt = K A DT/d • State-of-the-Art CMOS • Random logic • Max clock rate • 3 D Interconnected layers Man-made polycrystalline diamond could passively meet this requirement for thermal conductivity, K > 13 W/cm C. Note: KDiamond= 20 W/cm C @ 25 C, and also, KDiamond= 100 W/cm C @ 100 Kelvin

Polycrystalline Synthetic Diamond Courtesy of Norton Diamond Film Electro-Magnetic Arc Deposition of Synthetic Diamond

Visible &Thermal Images of Ceramic and Diamond MCMs Diamond Substrate Ceramic Substrate False Color IR Thermal Image @ 10 Watts per Chip Visible Light Image Still Air & Room Temperature

Cray Research J 90 Supercomputer

MCM Version of a Cray J 90

SGI/Cray Research J 90 Supercomputer Rack Mounted Flight Test Version Monitor Cray Hard Drive J 90 Cabinet Module Power Supply Aircraft Interface

All Computers Are Architecturally Two Dimensional The first two architectural dimensions are used for the circuit layout. The third architectural dimension is used for heat transfer.

25 KW 3 D Diamond Cube Design Stacked Diamond MCMs Form Cube Design Diamond MCM with Cu-Polyimide Interconnects Layers @ 625 Watts/MCM Moving the heat laterally through the diamond substrate to the edge fins can produce reliable operational conditions in this 3 D prototype demonstration system* at 2. 5 KW. Four 3 D MCM interconnected substrates make up this prototype system. Spray cooling (phase change) extracts the heat from the two edge fin areas. * “Thermal Analysis of Spray Cooled 3 D Interconnected Diamond Substrate MCMs: Comparison With Experimental Measurements”, Boudreaux, et al, IEEE on-line Journal Transactactions on Device and Materials Reliability, December 2004, pp 594 -604.

Schematic of 3 D Machine Photo of Sub-nanosecond Cycle Time Machine

Consider High Performance CMOS Operating at 1 Volt Bias • A 100 Watt chip requires 100 Amperes • Electromigration concerns limit current densities to < 105 A/cm 2 • Power distribution with distributed power converters is only 40 to 60% efficient, generating even more waste heat

How to Handle the Power Distribution? • Why are power converters so inefficient? – High values of RDS-on (>20 mili. Ohms) for semiconductor switches – Transformer inefficiency – poor ferrite performance – Switching power converters use low frequency <150 KHz • Is there a better way? – Integrated converters on chip at 100 -200 MHz – New semiconductor switch design – Nanoparticle ferrites for laminar transformers on chip

New Silicon NMOS 200 A@1. 2 V Switch Assembly Top view • Si NMOS via 2 m MOSIS • 0. 4 X 0. 4 cm 2 chip • Copper BCB Fine line Package Interconnect • 10 micron thick Cu • C 4 Flip Chip Bonded Side • 20 mil Cu-Invar-Cu Source view Contact Plane • 17 meter Gate length Chip Packaged Chip

400 Amperes @ 1. 2 Volts CMOS R DS(on)=179 micro. Ohms - 2 picosecond “Turn on” time - CMOS Gate length 17 Meters - Made with MOSIS technology - 93% efficient power converter Working prototype of switching power converter

Conclusions & Observations • Spray cooling has demonstrated the capability to handle power density > 150 W/cm 2 • Polycrystalline diamond is an excellent CTE matched heat spreader for Silicon ICs • Power converters “on-chip” are possible with efficiencies > 90% • On-chip currents of 200 to 400 Amperes are reliable at 1 volt • Random errors are a significant problem: – Redundancy (voting) is often not a viable solution with limited power – New “random error hardened” logic designs are required – Analog designs are now limited by these random level signals

A Case Study in Thermal Management and Power Distribution For a 3 D Interconnected High Performance Microelectronic System Paul J. Boudreaux Consultant & Senior Scientist University Research Foundation Laboratory for Physical Sciences College Park, MD 20740 boudreau@eng. umd. edu Tel: 301 -935 -6547

Laser Embedded Graphite Resistors in Diamond 1 K Ohm @ 500 Watts “As Grown” Diamond cut with a laser showing dark “residue” around circumference Laser induced graphite resistors in a diamond substrate with metal interconnect* * Boudreaux, et al, “Laser Induced Graphite Resistors in Synthetic Diamond”, International Journal of Microelectronics & Electronic Packaging, 1996, Volume 19 , pp 169 -177.

Moving & Expelling Heat • Low system overhead • Isothermal environment • Qj < 90 o. C • Die attach thermal impedance minimized • 3 D interconnections allowed • Clock speeds > 4 GHz • Bias voltage ~ 1 Volt • High thermal conductivity materials • CTE matching materials • High (>90%) efficiency power supplies • Phase change heat removal

WHY? The “best” switching supplies are limited by the switching device’s RDS-on impedance, typically 10 – 20 mili. Ohms. What if a switching transistor were made with a gate length of 50 meters instead of 2 – 3 microns? Then RDS-on would be < 20 micro. Ohms! At a clock speed of 200 MHz instead of 100 k. Hz, the L-C-R components are fully embedded and Integrated into die

déjà vu This is not the first time the industry has run into TMB • Vacuum tube – ENIAC’s MTBF =15 min Solution: Change Technology to transistors • Bipolar semiconductors – TTL, ECL, LSI~100 W/cm 2 Solution: Change Technology to CMOS • CMOS – ULSI > 100 W/cm 2 Solution: ? Today we are better situated with new materials and cooling technology to deal with the problem. NOTE: Even if CMOS is not used, thermal problem remains, i. e. SNL data. 3 D structures introduce a paradigm shift in thermal design because prior systems were architecturally two dimensional; the third dimension was the surface where the heat was extracted. In a true 3 D environment, this third dimension is used by interconnects, power distribution and bonding. New thermal concepts will be required to extract heat from such 3 D systems.