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The Continued Evolution of Re-Configurable FPGAs for Aerospace and Defense Strategic Applications Howard Bogrow The Continued Evolution of Re-Configurable FPGAs for Aerospace and Defense Strategic Applications Howard Bogrow

Abstract Present and future aerospace and defense applications continue to demand ever increasing performance, Abstract Present and future aerospace and defense applications continue to demand ever increasing performance, density, and above all flexibility from FPGAs. The Virtex families of re-configurable FPGAs provide the technology to meet these demands. Various members of these families are currently available in both COTs and SMD formats, as well as in radiation tolerant versions. Xilinx is also fully supporting a recently announced software tool that automates the implementation of TMR (Triple Modular Redundancy) into members of these FPGA families for mission critical applications. Xilinx has received government funding towards the development of a Single Event Immune Re-configurable FPGA (SIRF) with possibly strategic performance. This paper will focus on Xilinx currently available Virtex solutions, while also discussing Xilinx's future development efforts. There will also be some discussion of the various manufacturing flows utilized by Xilinx to address the stringent requirements of current and future space missions, as well as the latest package developments. Bogrow 2 MAPLD 2005/176

Xilinx Long-Term Commitment to Aerospace & Defense 1 st 90 nm Virtex-4 Platform FPGA Xilinx Long-Term Commitment to Aerospace & Defense 1 st 90 nm Virtex-4 Platform FPGA 0 4 Xilinx on 1 st. Rad tolerant Virtex-II Pro 130 nm Virtex-II 0 Mars Pro 2 1 st 150 nm Virtex-II Platform SEE Consortium 0 FPGA formed 0 Rad tolerant Virtex & SPROMs 9 Virtex million-gate 1 st 0. 35 & 0. 25 mm FPGAs 8 FPGAs 9 QML & ISO 9001 1 st rad tolerant devices 7 certifications 9 ISO 9002 5 certification 9 1 st Standard Military Drawing (SMD) 1 8 1 st device released to MIL-STD-883 qualified 9 8 Introduced 1 st field programmable gate array 5 (FPGA) 8 Xilinx 4 Founded 1985 1990 1995 2000 2005 Source: Company reports Bogrow 3 MAPLD 2005/176

Xilinx Technology Roadmap 180 nm • Leading SIA Roadmap 1 year Technology Leadership Virtex-E Xilinx Technology Roadmap 180 nm • Leading SIA Roadmap 1 year Technology Leadership Virtex-E – 150 nm, 130 nm and 90 nm – 300 mm wafers starting with Virtex-II and Virtex-E Extended Memory 150 nm SIA Virtex-II 130 nm • First 90 nm Spartan-3 family in Roa dm ap full production • First Virtex-4 devices now shipping Virtex-IIPRO 90 nm Virtex-4 Spartan-3 65 nm 45 nm First to 300 mm 1999 Bogrow 2000 First to 90 nm 2001 2002 4 2003 2004 2005 MAPLD 2005/176

Aerospace and Defense Virtex Mil Spec Products Next Generation 65 nm Virtex-4 90 nm Aerospace and Defense Virtex Mil Spec Products Next Generation 65 nm Virtex-4 90 nm Mil-Temp Space Grades Virtex-IIPRO Mil-Temp 130 nm Space Grades Virtex-II 150 nm Mil-Temp Space Grades 180 nm Rad Tolerant 220 nm “Rad by Design” Program 2003 Bogrow 2004 5 2005 MAPLD 2005/176 2006

Aerospace and Defense Qualifications Years from Commercial Production Qualification Closing the Gap with Commercial Aerospace and Defense Qualifications Years from Commercial Production Qualification Closing the Gap with Commercial 4 3 2 1 XC 300 0 XQ 4000 XL XC 4000 Rad. Hard By XC 4000 E Virtex-EVirtex-II Pro Design Program XQ 4000 XL EX Virtex-E Virtex-4 Virtex-II Pro Military Qualification Space Qualification Virtex-4 Program Goals FPGA Family Generations Bogrow 6 MAPLD 2005/176

Virtex-4 ASMBL™ Columnar Architecture th • Virtex 4 Generation advanced FPGA architecture • Enables Virtex-4 ASMBL™ Columnar Architecture th • Virtex 4 Generation advanced FPGA architecture • Enables “dial-In” resource allocation mix –Logic, DSP, BRAM, I/O, MGT, DCM, Power. PC • Enabled by Flip-Chip packaging technology –I/O columns distributed Bogrow throughout the device 7 MAPLD 2005/176

Three Virtex-4 Platforms LX FX SX Resource 14 -200 K LCs 12 -140 K Three Virtex-4 Platforms LX FX SX Resource 14 -200 K LCs 12 -140 K LCs 23 -55 K LCs 0. 9 -6 Mb 0. 6 -10 Mb 2. 3 -5. 7 Mb 4 -12 4 -20 4 -8 32 -96 32 -192 128 -512 240 -960 240 -896 320 -640 Rocket. IO N/A 0 -24 Channels N/A Power. PC N/A 1 or 2 Cores N/A Ethernet MAC N/A 2 or 4 Cores N/A Logic Memory DCMs DSP Slices Select. IO Density Bogrow Processor Cores 8 DSP MAPLD 2005/176

Process Technology Advances • Advanced 90 -nm process • 11 -Layer metallization Drain Metal Process Technology Advances • Advanced 90 -nm process • 11 -Layer metallization Drain Metal Connection Source Metal Connection – 10 copper + 1 aluminum • New Triple-Oxide Structures – Lower quiescent power consumption • Benefits: – – Best cost Gate Highest performance Source Channel Drain Lowest power Highest density • Over 1 million 90 nm FPGAs shipped Bogrow 9 MAPLD 2005/176

Dramatic Power Reduction in Virtex-4 Challenges - Static power grows with process generations - Dramatic Power Reduction in Virtex-4 Challenges - Static power grows with process generations - Transistor leakage current - Dynamic power grows with frequency - P = cv 2 f Power Consumpti on Virtex-4 cuts power by 50% nm 0 As G FP 13 • Measured 40% lower static power with Triple-Oxide technology • 50% lower dynamic power with 90 -nm • • Lower core voltage Less capacitance • Up to 10 x lower dynamic power with hard IP • Bogrow 50% Integration means fewer transistors per function 10 Frequency MAPLD 2005/176

Virtex-4 Configuration Features • Higher configuration speed – 100 MHz Serial & Parallel interface Virtex-4 Configuration Features • Higher configuration speed – 100 MHz Serial & Parallel interface – 66 MHz JTAG interface • • • CCLK available to users 256 bit AES security Configuration ECC ICAP and DRP support Dedicated configuration I/O bank • Enhanced partial reconfiguration • Compatible with previous 11 Bogrow TCK TDI TMS D[7: 0] TDO DOUT_B USY DIN MODE[2: 0] PROG_B DONE RDWR_B CS_B INIT CCLK MAPLD 2005/176

FPGA Radiation Tolerance TID Trends vs Product/Technology • 350 nm - XQ 4000 XL FPGA Radiation Tolerance TID Trends vs Product/Technology • 350 nm - XQ 4000 XL – 60 krad (Si) • 220 nm - XQVR (Virtex) – 100 krad (Si) • 150 nm - XQR 2 V (Virtex-II) – 200 krad (Si) • 130 nm – XQR 2 VP – 250 krad (Si) • 90 nm (Preliminary) – 300 krad (Si) Bogrow Process trends*: • Gate oxide continues to thin • Oxide tunnel currents increase • Gate stress voltage decreases *See “CMOS SCALING, DESIGN PRINCIPLES and HARDENING-BYDESIGN METHODOLOGIES” by Ron Lacoe, Aerospace Corp 2003 IEEE NSREC Short Course 2003 12 MAPLD 2005/176

SEE Consortium Platform FPGA Test Phases • Parallel Test Approach to accelerate product qualification SEE Consortium Platform FPGA Test Phases • Parallel Test Approach to accelerate product qualification • 3 SEE Consortium Tiger Teams: Fabric, Processor, Serial Transceiver Static Dynamic Mitigation (1 Q 05) (2 Q 05) (3 Q 05) FPGA Fabric and Static Cells V-2 pro Power. PC Processor & IP Special Solutions V-2 pro Multi-Gigabit Serial Transceivers Bogrow V-4 V-2 pro V-4 13 MAPLD 2005/176

Dose Rate Testing • Current Test Program • Historical Testing – XC 2 VP Dose Rate Testing • Current Test Program • Historical Testing – XC 2 VP 40 – XC 4036 XL • Work is funded by MDA • Testing is being done by a • Testing was done by Lockheed • Testing range of 1. 0 E 7 to 4. 0 E 11 (20 nsec pulse) tested • No data upset >1. 3 E 9 to >3. 0 E 9 • No latch-up beyond 4. 0 E 11 • – XCVR 300 E • • Testing done by ITT (MRC) • Testing range of 6. 3 E 7 to 3. 0 E 9 • No upset until > 4. 0 E 8 (nonepi) to >1. 0 E 9 (epi) • No latch-up beyond 3. 0 E 9 Bogrow • • • 14 consortium consisting of AFRL, Crane, Xilinx and Raytheon Initial tests were run July 2004 at Navsea Crane using 60 Me. V electron beam source utilized commercial Virtex-IIpro performance board and commercial V-IIpro parts Tests to compare RH (epi) performed in November 2004 at Navsea Crane No upset until > 3. 0 E 8 RH (epi) no POR until >1. 0 E 9 No Latch-up through >1. 0 E 10 MAPLD 2005/176

TMRTool • Software development tool to automatically implement TMR customer designs optimized for Xilinx TMRTool • Software development tool to automatically implement TMR customer designs optimized for Xilinx FPGAs • Result of Xilinx/Sandia National Labs partnership – Released to Production in Sept 2004 • Support all design entry methods and HLLs – NGO & NGC based input – EDIF based output • OS Support Bogrow – Windows 2000/XP GUI Support – Windows/UNIX PERL Command Line Support 15 • Supports ISE 5. 2 i, 6. 1 i, 6. 2 i MAPLD 2005/176

TMRTool Netlist Flow Xilinx Design Flow Bogrow 16 MAPLD 2005/176 TMRTool Netlist Flow Xilinx Design Flow Bogrow 16 MAPLD 2005/176

Rad. Hard by Design Program SEU Immune Reconfigurable FPGA (SIRF) Configuration Memory Block Memory Rad. Hard by Design Program SEU Immune Reconfigurable FPGA (SIRF) Configuration Memory Block Memory Control Logic Clocking & Clock Mgmt Logic Fabric DSP Fabric Rocket. IO™ Multi-Gigabit Transceiver Select. IO Power. PC™ Virtex-4 Silicon Floorplan Phase-1: Design Feasibility, Test Chip Phase-2: Chip Development Phase-2 A: Advanced Features Bogrow 17 MAPLD 2005/176

SIRF Radiation Goals Bogrow 18 MAPLD 2005/176 SIRF Radiation Goals Bogrow 18 MAPLD 2005/176

Advanced Packaging • CG 717 o 35 x 35 mm body, 1. 27 mm Advanced Packaging • CG 717 o 35 x 35 mm body, 1. 27 mm pitch, cavity-up o Footprint compatible with the BG 728 o Developed for the 2 V 3000 o Wire Bond, gold o Au-Sn lid (hermetically sealed) • CF 1144 o 35 x 35 mm body, 1. 00 mm pitch o Footprint compatible with the FF 1152 o Developed for the 2 V 6000 o Flipchip with high lead balls, MSL 1 Bogrow 19 MAPLD 2005/176

Enhanced Flow – In Development Bogrow 20 MAPLD 2005/176 Enhanced Flow – In Development Bogrow 20 MAPLD 2005/176

Summary • Virtex-4 architecture and design methodology • • Bogrow enables rapid development of Summary • Virtex-4 architecture and design methodology • • Bogrow enables rapid development of Platformspecific FPGAs with embedded cores Advances in 90 nm chip design resulted in optimized performance, lower power, and firstsilicon success of Virtex-4 SEE Consortium primary vehicle for radiation characterization testing (US and European) Rad Tolerant program will continue with concurrent phase-in of Rad Hard by Design program Advanced packaging and enhanced process flows integral part of overall development efforts 21 MAPLD 2005/176