TFB hardware status 7 9 06 some things to

TFB hardware status – 7/9/06 some things to discuss and questions to address TFB PCB layout status LV power, connector and cabling signal connectors (RJ 45 + what to use for trig. ) slow control/monitoring functionality component procurement timescale Mark Raymond - 7/9/06

TFB mounting plan for ECAL TFB cooled Al mounting plate to Si. PM thermal gap filler TFB mounted on cooled Al plate with cutouts through which Si. PM cables are fed min. coax connectors (and other connectors) on top surface chips to be cooled on bottom surface, in thermal contact with plate thermal gap filler allows for differences in chip thicknesses power regs. on top side – dissipating heat to board – so will need to provide good thermal pathway to mounting plate in this area of TFB coax socket ~2 mm dia. Mark Raymond - 7/9/06 terminated coax cable (1. 3 mm dia. )

TFB PCB layout status coaxial connectors on top surface ~ 9 cm trip-t, FPGA, HVtrim. DACs on bottom (can be thermally coupled to cooling) ADCs, regulators, connectors on top surface 6 routing layers top, bottom + 4 internal + power and ground layers so maybe 10 layers overall? ~ 14. 5 cm ~ 16 cm signal routing ~ complete not yet implemented FPGA config. cct, JTAG I/F, LEDs, mounting holes, test points, power and ground planes, … board may have to grow in the long direction – maybe back to 16 cm or more – is that acceptable? Mark Raymond - 7/9/06

TFB onboard LV power regulators supply after reg. component 1. 5 -1. 7 1. 2 LP 38843 ES-1. 2 circuitry supplied power on TFB [W] <3 FPGA core 3. 6 <0. 5 trip-t 1. 3 ~1. 05 2. 5 A 2. 95 - 3. 1 current [A] FPGA 2. 5 2. 6 LP 3856 ES-2. 5 D 3. 8 3. 3 D LP 3856 ES-ADJ ~0. 95 FPGA I/O 3. 1 5. 5 5 A LP 3856 ES-5. 0 <0. 2 ADCs / HVtrim. DACs 1 5. 7 return dropout depends on current – should prob. take worst case 11. 6 all TO 263 -5 packages with shutdown inputs (=> one line from outside (where? ) could be used to power down an individual TFB) some other small regulators on board to supply PROM, slow control cct. , but low power requirements and can take inputs from above supply levels Mark Raymond - 7/9/06

power connector propose 26 way, dual row, 0. 1” pitch MOLEX connector, 3 A/pin rated doesn’t have to be but this is relatively compact HV HV 1. 2 sense 2. 5 sense 3. 3 sense 5 5 gnd gnd gnd shutdown 5 sense some questions who provides the cabling – do we make it ourselves? 48 TFBs per power group – how/where do we split the incoming power lines to feed individual TFBs? how can we make use of regulator shutdown to disable individual TFBs? fuses? (regulators include overcurrent/overtemperature protection) HV only decoupled on entering board – no onboard disconnect switch at present. A shorted Si. PM will draw current but series resistance will limit. voltages after regulation on TFB – actual levels will be higher use 2 pins/supply above distribution an example – not final Mark Raymond - 7/9/06

signal connectors data screened RJ 45 - 4 twisted pairs data in data out 100 MHz clock triggering line (spill start, spill no. , cosmic, calibration? ) trigger out only one twisted pair/TFB has to eventually feed RJ 45 on GTM can we use small connector on TFB and merge signals into RJ 45 cable using an intermediate board? what small connector can we use? any ideas? firewire? Mark Raymond - 7/9/06

slow control (monitoring) single channel AD 5321 DAC 0 -> 5 V, 12 bit resolution, for trip-t electronic calibration 8 channel AD 7998 ADC, 0 -> 4. 096 (external AD 1584 ref. ), 12 bit resolution, for monitoring both chips with I 2 C interface controlled by FPGA allocation of ADC inputs 1 2 3 4 5 6 7 8 1. 2 V supply 2. 5 V supply 3. 3 V supply 5 V supply (divided down) HV global (divided down) electronic cal voltage (divided down) LM 335 temperature sensor on TFB pcb not yet allocated 9 is this enough? do we need connector for external temperature sensor? Mark Raymond - 7/9/06

active component procurement compnt. function AD 9201 Spartan 3 PROM AD 5308 FDV 303 N AD 5321 AD 7998 AD 1584 LP 38843 S-1. 2 LP 3856 ES-2. 5 LP 3856 ES-5. 0 LP 3856 ES-ADJ LM 335 BSN 20 mosfets tript O/P ADC FE-FPGA for FPGA config. 8 bit HVtrim. DAC CAL FET CAL DAC 12 bit ADC monitoring Vref 1. 2 V reg. 2. 5 V reg. 5 V reg. 3. 3 V reg. temp. sensor I 2 C level shift supplier/comments 4 tript #/TFB Fermilab can supply 100 packaged and tested chips, $20 each (payment details need attention) 2 1 1 8 16 1 1 1 1 2 Farnell in stock at IC RS Farnell Farnell Farnell + some others Need to think about quantities to buy now, may need to 2 nd source if stock problems what budget to use? do we need to worry about Ro. HS compliance? Mark Raymond - 7/9/06

timescale still a few weeks work left on layout need to procure components now (for ~ 20 boards) suggest to produce 2 boards quickly - hopefully by end October produce more, on slower timescale, after no major (electrical) problems identified testing needs some thought…. Mark Raymond - 7/9/06

Mark Raymond - 7/9/06

Trip-t and TFB status Trip-t brief description of internal architecture and interfaces proposed Trip-t operation at T 2 K Si. PM connection, gain and discriminator threshold considerations Results from latest Tript version linearity and discriminator measurements TFB prototype status results from prototyping elements ADC functionality and test results HVtrim functionality and test results Calibration circuitt description and test results TFB layout status TFB firmware status future plans DRAFT TALK – NOT YET FINISHED Mark Raymond - 7/9/06

Trip-t single channel front end architecture very simplified – neglecting features not relevant to ND 280 operation preamp integrate/reset gain adjust 1, 2, 3, … 8 analogue pipeline Qin 1 p. F 3 p. F gain 1 or 4 discriminator x 10 disc. O/P Vth reset only preamp gain affects signal feeding discriminator – no fine control (x 1 or x 4) Vth common to all channels on chip analog bias settings, gain, Vth, programmable via serial interface Mark Raymond - 7/9/06

Trip-t full chip simplified and neglecting features not relevant to operation in ND 280 48 top 16 IP/s bottom 16 I/Ps 32 analog outputs 32 front end chans 32 analogue memory (pipeline) control 32 32: 1 analog MUX serial analog output control top 16 disc. O/Ps bottom 16 disc. O/Ps bias, control, reset dig. MUX 32: 16 control top or bottom 16 disc. O/Ps serial programming interface, bias gen. , control interface, … dig. control 32 channel chip -> 1 serial output, 48 deep analogue pipeline to store sampled front end outputs (note: pipeline operated using 2 timeslices/preamp integration period, so length reduced to 23 see http: //www. hep. ph. ic. ac. uk/~dmray/pdffiles/FIFOtalk_1_3_06 for detailed explanation) have to select either top or bottom 16 disc. O/Ps to transmit off-chip ~ 12 digital control/programming inputs, 16 disc. outputs => ~ 30 I/O lines/chip (2. 5 V CMOS) Mark Raymond - 7/9/06

Trip-t operation at T 2 K Proposed mode of Trip-t operation for beam spill data acquisition is as follows during spill integrate signal for each bunch and store result in pipeline* (15 timeslices for 15 bunches) timestamp high gain channel discriminator outputs that fire after spill continue running in same way, for a while, to catch late signals (m decay) readout entire contents of pipeline assemble data block containing hit timestamps and all digitized analogue data and transmitting all info in this way allows histogramming of single p. e. events to monitor Si. PM gain vast majority of data is pedestal + single/double p. e. hits only start of spill 5. 25 ms spill period at this time trip-t switches to inter-spill operational mode (cosmic trigger) end of spill 2. 8 ms after spill active period Mark Raymond - 7/9/06 74 ms (23 cell) readout period (if O/P mux running at 10 MHz)

Tript for ND 280, gain considerations need ~ 500 p. e. dynamic range, while simultaneously discriminating signals at the ~ 1 p. e. level can’t be done with one gain range => split signal between high/low gain ranges (channels) Signal shared between Cadd, Chi and Clo (also some strays), Chi/Clo = high/low gain ratio HVglobal simplified single Si. PM channel schematic Chi 100 p. F trip-t 1 MW Clo 10 p. F thin coax 50 W Si. PM HVtrim Cadd 330 p. F Choose Cadd to match final Si. PM gain (330 p. F about right for 5 x 105) Cadd also helps with gain discontinuity when hi gain channel saturates (see http: //www. hep. ph. ic. ac. uk/~dmray/pdffiles/tript_talk_1_3_06) don’t know what final Si. PM gain will be, but assume production devices will be quite well matched in any case will have individual channel gain adjustment by HVtrim. DACs Mark Raymond - 7/9/06

Discriminator threshold (Vth) considerations 1 p. F analogue pipeline Qin reset disc. O/P x 10 Vth only relevant to the 16 high gain channels - remember only 16 channels can be selected for transmission off-chip, so just arrange for these to be the high gain channels (Vth also applied to low gain channels, but we don’t need to look at the outputs of these) Vth needs to be set high enough to prevent single p. e. events triggering discriminator (otherwise single p. e. triggers will dominate and will lose ability to timestamp real signals) uncertainty in threshold setting given by spread in discriminator turn-on curves across chip can choose high gain channel value (external capacitor division ratio) but trade-off between threshold adjustment range and uncertainty in threshold value Mark Raymond - 7/9/06

Gain and gain ratio considerations (1) single tript channel 1 p. F analogue pipeline Qin reset disc. O/P x 10 Vth ~ 1 V dynamic range available at preamp O/P ~ similar voltage range at x 10 amp O/P ~ similar disc. thresh. voltage adjustment range 2. 5 V CMOS so can assume dynamic ranges of internal circuits ~ 1 V this has implications for discriminator threshold range if want 0 – 5 p. e. adjustment range then 5 p. e. ≡ 1 V at x 10 O/P => 1 V ≡ 50 p. e. at preamp O/P so high gain channel will saturate at ~ 50 p. e. this translates to threshold uncertainty ~ +/- 0. 5 p. e. (measured – see later) Mark Raymond - 7/9/06

Gain and gain ratio considerations (2) HV(TFB) simplified single Si. PM channel schematic Chi 100 p. F 1 MW thin coax 50 W Clo 10 p. F Si. PM HVtrim Cadd 330 p. F So discriminator threshold range adjustment 0 -> 5 p. e. High gain channel saturates at 50 p. e. Choose Chi/Clo so low gain channel saturates at 500 p. e. Note: These values are examples and can change, but need to take care with threshold adjustment range/uncertainty trade-off Mark Raymond - 7/9/06 Trip-t

Latest Trip-t test results from final version 2 nd (final) tript version very similar to 1 st minor architecture change to improve O/P stage linearity version 2 linearity clearly better but still some gain reduction for small signals Þ will need electronic calibration to correct for linearity Mark Raymond - 7/9/06

Tript V 2 linearity(1) all 16 channels, hi and lo gains higain cahnnels component values chosen for Si. PM gain ~ 5 x 105 (Chi = 100 p. F Clo=10 p. F, Cadd=330 p. F) lo gain saturates at ~ 40 p. C (500 p. e. ) logain channels Mark Raymond - 7/9/06 hi gain saturates at ~ 4 p. C (50 p. e. )

Tript V 2 linearity(2) log-log plot of same data 10: 1 gain ratio means gain range change occurs where logain signal size already large so no S/N problems higain channels logain channels Mark Raymond - 7/9/06

Tript V 2 discriminator measurement count the no. of times the discriminator fires for 1000 preamp integration periods sweep the injected signal size discriminator curves for all 16 higain channels for 5 x 105 1 p. e. -> 0. 08 p. C pk-pk width ~ 1 p. e. also for this measurment so +/- 0. 5 p. e. precision can improve precision but remember trade-off with adjustment range 1 p. e. Mark Raymond - 7/9/06 2 p. e.

Tript V 2 discriminator timewalk significant timewalk and chanto-chan spread for small signals can set threshold at 1. 5 p. e. and discriminator will fire, but timestamp for low amplitude signals will not be reliable OK for signals > ~ 3 p. e. can correct for timewalk off-line 1 2 3 p. e. (1 p. e. = 80 f. C (5 x 105) Mark Raymond - 7/9/06

TFB (Tript Front-end Board) prototype status main functionality: 4 Tript’s/TFB => 64 Si. PM channels (for ECAL) individual programmable HVtrim (5 V range) for each Si. PM channel tript O/P signal digitisation front end electronic calibration FPGA to program tript, sequence operation, timestamp hits, control digitisation, format and transmit data, … local LV power regulation prefer to prototype designs for individual functions as much as poss. before committing to final TFB prototype results here for on-board ADC, HVtrim and electronic calibration circuits Mark Raymond - 7/9/06

prototyping elements of TFB cal cct Si. PM AD 9201 Tript HVtrim. DAC miniature coax and connectors necessary to proove as much of TFB circuitry as possible before committing to layout helps to identify where extra layout care is needed improves chances of TFB prototype working successfully Mark Raymond - 7/9/06

Si. PM -> TFB connection - details HVglobal 47 k 50 V, 0402 220 p. F 50 V 0402 47 k 50 V, 0402 cal test pulse 10 p. F 100 V, 0603 Si. PM coax sheath not DC coupled to GND 1 k LV, 0402 significant no. of passives/channel – need careful, high density layout trip-t 100 p. F 100 V 0603 51 R LV 0603 100 n. F LV 0402 330 p. F 100 V 0603 10 p. F 100 V 0603 HVtrim(0 -5 V) HVglobal: common to all Si. PM channels on TFB HVtrim: individual for each Si. PM channel, 5 V adjustment range (choice of 8/10/12 bit DAC precision) HVtrim applied to coax sheath – AC but not DC coupled to GND Mark Raymond - 7/9/06

ADC for the TFB AD 9201 – used by D-zero dual-channel => 2 tript’s/ADC 28 pin SSOP package separate analog and digital supplies 5 V analogue – needed to accommodate tript O/P range 3. 3 V digital Mark Raymond - 7/9/06

tript linearity measured with AD 9201 analog supply and ADC reference voltage configuration optimised so that tript output signals well matched to 10 bit ADC range Mark Raymond - 7/9/06

Si. PM signals measured with tript/AD 9201 Russian Si. PM: gain 5. 6 x 105 275 ns preamp integration period 100, 000 events in each spectrum ~ 10 ADC units / p. e. => 0. 1 p. e. ADC resolution Mark Raymond - 7/9/06

HV trim circuit for TFB HVglobal 51 R LV 0603 Si. PM coax sheath carries HVtrim voltage 1 k LV, 0402 HVtrim(0 -5 V) 100 n. F LV 0402 8 channel DAC chip => 2 / tript, 8 / TFB 8/10/12 bit versions available identical chips, just different resolution (price difference but negligible to us) TSSOP 16 pin SM package serial interface to program (from FE FPGA) output voltage variable 0 -> 5 V 20 m. V resolution for 8 bit version Mark Raymond - 7/9/06

TFB HV trim circuit linearity 8 bit DAC version used here single DAC channel measurement Mark Raymond - 7/9/06 gives 20 m. V precision for 5 V range should be enough?

TFB HV trim circuit with Si. PM LED spectra for device with nominal 47. 5 V operating voltage showing effect of HVtrim circuit 5 Volt range for HVtrim gives overall range 45 – 50 Volts (when combined with HVglobal) Mark Raymond - 7/9/06

CAL circuit for TFB to 16 trip-t Si. PM channels before gain splitting capacitors 10 p. F 4 CAL lines feeding every 4 th channel Vcal (0 – 5 V) (use another AD 5308 DAC here) from FE-FPGA discrete MOSFETs Mark Raymond - 7/9/06

CAL circuit test results with tript/AD 9201 16 high gain chans tript multiplexed analog output stream for different DAC values for one CAL test input – sampled with scope tript MUX (and ADC) running at 5 MHz 16 low gain chans substantial crosstalk – but only after high gain channels beyond saturation Mark Raymond - 7/9/06

CAL circuit test results with tript/AD 9201 linearity measured for one Si. PM channel using external test pulse and CAL circuit -> close correspondence (also using AD 9201) Mark Raymond - 7/9/06

TFB elements prototyping summary tript output ADC, Si. PM HVtrim DAC circuit and electronic chain calibration circuit all prototyped and tested no major problems encountered can now proceed to lay out the TFB prototype with confidence that at least these elements should function OK. Mark Raymond - 7/9/06

TFB layout status – 10 cm x 16 cm HVtrim 16 Si. PM I/Ps and passives HVtrim CAL cct Tript AD 9201 footprint Mark Raymond - 7/9/06 FPGA footprint high density Si. PM I/P layout complete – gives confidence that size target ~ achievable still much left to do (e. g. FPGA dig. signals routing, power regs. , connectors (power and control), slow control interface, …. .

TFB mounting ideas (ECAL) TFB cooled Al mounting plate to Si. PM thermal gap filler TFB mounted on cooled Al plate with cutouts through which Si. PM cables are fed min. coax connectors (and other connectors) on top surface chips to be cooled on bottom surface, in thermal contact with plate thermal gap filler allows for differences in chip thicknesses power regs. on top side – dissipating heat to board – so will need to provide good thermal pathway to mounting plate in this area of TFB coax socket ~2 mm dia. Mark Raymond - 7/9/06 terminated coax cable (1. 3 mm dia. )

TFB interfaces 4 LVDS pairs (RJ 45 type connector and cable – should be screened) Clocks input: 100 MHz, 1 Hz, Spill/Cosmic trigger Data input Data output RF clock ? (maybe not needed) slow control TBD (maybe just a connector to plug-on micro-controller based circuit? ) Power < ~100 V +2. 5 +5 +3. 3 +1. 2 Mark Raymond - 7/9/06 small ~ 0. 5 A ~ 0. 2 A TBD Si. PM HV tript and FPGA I/O ADC analogue and HVtrim DAC ADC digital and FPGA I/O FPGA core

some data volume numbers for programming tript: ~ 900 kbits for 50 k channels HVtrim DACs: 8 bits res’n x 50 k chans = 400 kbits for raw spill data readout (data only) assume 23 integration periods 4 tript’s / TFB 32 channels/tript (hi and logain) 10 bit ADC => ~30 k bits /TFB /spill + hit timestamp data and associated hit channel addresses Mark Raymond - 7/9/06

planning Plans for this year (2006) 1 st TFB prototype to be produced by end October in parallel produce sufficient firmware for characterization detailed electrical characterization by beginning 2007 Plans for next year (2007) vertical slice test (1 st quarter) TFB prototype with photosensors, RMM and MCM prototypes review requirements and design 2 nd (final) TFB prototype for ECAL produced and tested by end of year Mark Raymond - 7/9/06