Скачать презентацию Tallinn University of Technology Raimund Ubar Computer Engineering Скачать презентацию Tallinn University of Technology Raimund Ubar Computer Engineering

359c9d000c6381dd58e9d7713be00d0e.ppt

  • Количество слайдов: 16

Tallinn University of Technology Raimund Ubar Computer Engineering Department Founded as engineering college in Tallinn University of Technology Raimund Ubar Computer Engineering Department Founded as engineering college in 1918, TTU acquired university status in 1936. TTU has about 9000 students and 1209 employees, offering engineering and economics diploma studies, bachelor, master and doctorate degree programmes. Academic part of the university is organised into § 8 faculties, § 30 departments and 108 chairs, § 7 centres and § 9 affiliated institutions.

Research Topics • Computer science: Decision Diagrams • Test Pattern Generation Hierarchical Approaches Defect-Level Research Topics • Computer science: Decision Diagrams • Test Pattern Generation Hierarchical Approaches Defect-Level Testing • Simulation of Circuits and Systems Fault Simulation (SAF, functional faults, delays) Dynamic (multivalued) Simulation • Built-In Self-Test Hybrid BIST Functional BIST • Hardware accelerators for Fault Simulation

European projects History (1992 -2000): • TEMPUS: Digital Design based on PLDs (1992 -95) European projects History (1992 -2000): • TEMPUS: Digital Design based on PLDs (1992 -95) • EUROCHIP (1993 -1996) - EUROPRACTICE (1996 -) • PECO: EEMCN - East European Microelectronics Cooperation Network (1993 -96) • COPERNICUS: FUTEG - Functional Test Generation (199497) • ESPRIT: ATSEC - Advanced Test Generation and Testable Design Methodology (1994 -96) • COPERNICUS: SYTIC - System Design Training (1996 -98) • COPERNICUS: VILAB - Microelectronics Virtual Laboratory for Cooperation in Research (1998 -2002)

Current European Projects • FRAMEWORK V: REASON - Research and Training Action for System Current European Projects • FRAMEWORK V: REASON - Research and Training Action for System On Chip Design (2002 -2004) • FRAMEWORK V: e. Vikings II - Establishment of the Virtual Centre of Excellence for IST RTD in Estonia • SOCRATES 2 Thematic Network Project THEIERE -Thematic Harmonisation in Electrical and Information Enginee. Ring in Europe • SOCRATES 2 Thematic Network Project ECET - European Computing Education and Training (2002 -2004) • EUROPRACTICE

Our Partners TTU cooperates with about 20 -30 universities KTH LIU TTU Jonköping USA: Our Partners TTU cooperates with about 20 -30 universities KTH LIU TTU Jonköping USA: Michigan U Dresden Costa Rica Indonesia Grenoble Ilmenau Darmstadt Stuttgart Torino East. Kharkov and Middle. Europe

Hierarchical Test Generation Tool Logic Synthesis Scripts Design Compiler (Synopsys Inc. ) Gate Level Hierarchical Test Generation Tool Logic Synthesis Scripts Design Compiler (Synopsys Inc. ) Gate Level Descriptions y 1 y 2 RTL Model (VHDL) FU Library (DDs) a R 1 · RTL DD Synthesis R 2 M 2 · y 4 0 RTL DD Model Test patterns d R 2 2 Hierarchical ATPG * #0 1 SSBDD Synthesis SSBDD Models of FUs M 3 b · 0 y 3 0 y 1 1 1 Modules or subcircuits are represented as word -level DD structures 2 3 R 1 + R 2 IN R 1 y 2 y 4 c + M 1 · IN y 3 0 1 R 1* R 2 IN* R 2 e R 2 ·

Turbo-Tester Tool Set Fault models: Levels: Gate Macro Design Deterministic Random Genetic Methods: Stuck-at-faults Turbo-Tester Tool Set Fault models: Levels: Gate Macro Design Deterministic Random Genetic Methods: Stuck-at-faults Stuck-opens Delay faults Methods: Single fault Parallel Deductive Test Generation BIST Simulation Test Fault Simulation Fault Location Fault Table Fault Diagnosis Methods: BILBO CSTP Store/Generate Test Optimization

Hybrid BIST for Multiple Cores Embedded tester for testing multiple cores Hybrid BIST for Multiple Cores Embedded tester for testing multiple cores

Optimized Multi-Core H-BIST Pseudorandom test is carried out in parallel, deterministic test - sequentially Optimized Multi-Core H-BIST Pseudorandom test is carried out in parallel, deterministic test - sequentially

Applet for Learning RT L Test For learning problems of RTlevel digital design and Applet for Learning RT L Test For learning problems of RTlevel digital design and test: • Design of data path and control path • Tradeoffs between speed & HW cost • RT-level simulation • Fault simulation • Test generation • DFT and BIST

Virtual Lab: Tool integration Cooperation with Fh-IIS, DTU, LIU, IISAS, WUT Behavioral level VHDL Virtual Lab: Tool integration Cooperation with Fh-IIS, DTU, LIU, IISAS, WUT Behavioral level VHDL description (EAS/IIS) 1 MOSCITO USER (EAS/IIS) High-level VHDL description (EAS/IIS) 2 Logic synthesis 7 Gate-level EDIF High-level synthesis RTL VHDL description 8 EDIF-ISCAS VHDL-DD ( converter. TTU) 4 EDIF-SSBDD High-level DD model 3 Commercial CAD software ISCAS benchmarks Schematic entry converter(TTU) ISCAS etlist n SSBDD model 5 Hierarchical ATPG(TTU) converter(TTU) 6 Turbo Tester (TTU) 9 ISCAS-SSBDD converter(TTU) 10 Test patterns exchange interface Def. Gen (IIN) 11 University software Functional test (EAS/IIS)

Proposal: Ingredients of So. C test 1. Functional test to test the system (WP Proposal: Ingredients of So. C test 1. Functional test to test the system (WP 1) 2. BIST, embedded test for IP cores (WP 3)

Tallinn University of Technology • WP 1. High-level modeling and simulation - Methods for Tallinn University of Technology • WP 1. High-level modeling and simulation - Methods for automated generation of functional test at the system-level for verification purposes. - We have previous experience in: - High-level modeling and simulation - High-level test pattern generation - Design error identification at the logic level.

Tallinn University of Technology • WP 3. Setting up a Virtual IP library - Tallinn University of Technology • WP 3. Setting up a Virtual IP library - Solutions for automated synthesis of the test infrastructure to IPs. - Novel hybrid BIST strategies - Functional BIST - Web based e-learning tools for teaching IP test standards like Boundary scan and P 1500.

Artec Design Group • Artec Design Ltd. founded in 1998 is a successful Estonian Artec Design Group • Artec Design Ltd. founded in 1998 is a successful Estonian SME empoying more than 30 people. • In 2001, the company was selected to top ten in the Central European Technology Fast list. • The field of the Artec company is designing hardware, ASICs, embedded software and factory information systems. • The company has been involved in a number of national and European level research projects.

Artec Design Group • VPNow: an IP core for cryptographic network processing. – It Artec Design Group • VPNow: an IP core for cryptographic network processing. – It allows any system with PCI interface to connect using the IPSec encryption standard. – Possible to send new, ipv 6 internet protocol packets via existing ipv 4 networks and vice-versa. • A network-ready, full-function compact 486 motherboard with an award-winning Single Component Computer Mach. Z.