Скачать презентацию Tablegen Deep Dive Reed Kotler MIPS Technologies Inc Скачать презентацию Tablegen Deep Dive Reed Kotler MIPS Technologies Inc

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Tablegen Deep Dive Reed Kotler MIPS Technologies, Inc 12 April 2012 1 © 2011 Tablegen Deep Dive Reed Kotler MIPS Technologies, Inc 12 April 2012 1 © 2011 MIPS Technologies, Inc. All rights reserved.

Overview Introduction to Table. Gen Providing additional information to available documentation Help improve Table. Overview Introduction to Table. Gen Providing additional information to available documentation Help improve Table. Gen definition Grammars and language definition Develop more documentation and examples Ability to further define compiler through Table. Gen 2 © 2011 MIPS Technologies, Inc. All rights reserved.

Why Table. Gen? Describes target machine to LLVM Architecture information typically duplicated and spread Why Table. Gen? Describes target machine to LLVM Architecture information typically duplicated and spread throughout machine’s ISA/ABI documents Succinctly represents target description Description used by compiler, assemblers and disassemblers, etc. Simplifies maintainability and reliability due to modular design Table. Gen documents (located at llvm. org) "Table. Gen Fundamentals“ "The LLVM Target-Independent Code Generator“ "Writing an LLVM Compiler Backend" 3 © 2011 MIPS Technologies, Inc. All rights reserved.

Overview of Table. Gen Processing Two pass processing of description files First pass is Overview of Table. Gen Processing Two pass processing of description files First pass is essentially a template/macro preprocessor. Its output is an expanded set of class and record (data) definitions. There are many second passes (application specific backends). These produce various. inc files used by the target dependent backends Each backend processor assigns its own meaning to expanded class and record data, as for example an application that reads XML does 4 © 2011 MIPS Technologies, Inc. All rights reserved.

Overview of Table. Gen Processing (continued) First phase is text macro processor important exception: Overview of Table. Gen Processing (continued) First phase is text macro processor important exception: The information collected during record creation is available to the application specific backend using it. For each expanded record, the list of classes which it was derived from is preserved for use by the application specific backends. This is an important detail and something not usually present in a macro or template preprocessor. Example: all records derived from a class can be collected by tool and data can be distributed throughout definitions and later, this can be collected back together. i. e. the set of register or instruction defns. All known backends for tablegen are linked into llvmtblgen. Full set can be see by llvm-tblgen --help. 5 © 2011 MIPS Technologies, Inc. All rights reserved.

Where to Find Additional Information Test_data for Table. Gen tool test/tablegen/*. td Any target-specific Where to Find Additional Information Test_data for Table. Gen tool test/tablegen/*. td Any target-specific compiler. td file Information available on code. google. com http: //code. google. com/p/alt-llvm-tablegen/ This presentation Other sample code Google code project is also scratch pad for future ideas Experimentation Code samples and clarified documentation Goal is to improve llvm. org documentation with minimal disruption 6 © 2011 MIPS Technologies, Inc. All rights reserved.

Learning More About Table. Gen Run only the first phase of llvm-tblgen. Some options: Learning More About Table. Gen Run only the first phase of llvm-tblgen. Some options: -print-records(default) -print-enums -class= -print-sets read through the. td files in the llvm source tree Target template. td files. Lib/include/llvm/target/*. td Target-specific. td for familiar machines Lib/target/*/*. td Study the sample code of the talk All. td files from the talk are in a tar file at the conference website can be found in the alt-llvm-tablegen project at googlecode Contribute to the project alt-llvm-tablegen 7 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 4. td // pure data. anonymous type. def rec 1 { int Example: talk 4. td // pure data. anonymous type. def rec 1 { int i = 1; string h = "hello"; } // data record of type class 1 { int i = 1; string h = "hello"; } def rec 2 : class 1; // simple parameterized with default parameters class 2 { int i = p 1; string h = p 2; } def rec 3 : class 2 <5> 8 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 4 a. out (classes) ------- Classes --------class 1 { int i = Example: talk 4 a. out (classes) ------- Classes --------class 1 { int i = 1; string h = "hello"; string NAME = ? ; } class 2 { int i = class 2: p 1; string h = class 2: p 2; string NAME = ? ; } 9 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 4 a. out (defs) ------- Defs --------def rec 1 { int i Example: talk 4 a. out (defs) ------- Defs --------def rec 1 { int i = 1; string h = "hello"; string NAME = ? ; } def rec 2 { // class 1 int i = 1; string h = "hello"; string NAME = ? ; } def rec 3 { // class 2 string class 2: p 2 = "hello"; int i = 5; string h = "hello"; string NAME = ? ; } 10 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 5. td class forward; // could be empty class or forward declaration Example: talk 5. td class forward; // could be empty class or forward declaration class t parm 1> { list f = parm 1; } class forward { string n = parm 1; } def one: forward<"cat">; def two: forward<"dog">; 11 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 5. td (cont) class empty; def e 1 : empty; def e Example: talk 5. td (cont) class empty; def e 1 : empty; def e 2 : empty; // or is it? class empty { int i; } def e 3: empty; 12 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 6. td class node; def na : node; def nb : node; Example: talk 6. td class node; def na : node; def nb : node; def nc : node; def prim_types { bit b; bit t = 1; bit f = 0; int i; int j = 0 b 1100; // binary representation int k = 0377; // octal representation 13 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 6. td int l = 0 xface; bits<3> i 3 = 0 Example: talk 6. td int l = 0 xface; bits<3> i 3 = 0 b 110; bits<4> j 4 = {1, 0, 1, 1}; string s 1; string s 2 = "hello"; list li = [1, 2, 3, 4]; list strings = ["house", "road", "basement", "shed"]; list ln = [na, nb, nc]; dag d 1 = (na 1, 2 ); dag d 2 = (na (nb 1, 2), nc, 4); 14 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 6. td code c; // similar to python int main() { printf("hello world n"); } }] ; string s_code = [{ #include int main() { printf("hello world n"); } }] ; } 15 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 7. td / examples of let class c 1 { int i Example: talk 7. td / examples of let class c 1 { int i = 1; } / def rec 1 : c 1 { let i = 2; } class int int } 16 c i j k { = 1; = 2; = 3; © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 7. td def rec 1: c; let i = 2 in def Example: talk 7. td def rec 1: c; let i = 2 in def rec 2: c; let i = 3, j=6, k=9 in { def rec 3: c; def rec 4: c; } let i=100 in { def rec 5: c; let j=200 in { def rec 6: c; let k=300 in def rec 7: c; } } 17 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 8. td // bits. very useful for encoding. def basic_bits { bits<5> Example: talk 8. td // bits. very useful for encoding. def basic_bits { bits<5> x = 0 b 11001; bits<5> y = {1, 0, 0}; bits<3> z = y{0 -2}; bits<10> zz; let zz{0 -4} = x; let zz{5 -9} = y; bits<10> zzz; let zzz{4 -0} = x; let zzz{9 -5} = y; bit b = 1; bits<5> zzzz; let zzzz{0} = b; let zzzz{4 -1} = 5; bit b 1 = zzzz{0}; } 18 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 9. td // Example of multiple inheritance class c 1 { int Example: talk 9. td // Example of multiple inheritance class c 1 { int i 1 = 1; } class c 2 { int i 2 = 2; } class c 3: c 1, c 2; def d 1: c 1, c 2; def d 2: c 3; 19 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 10. td // // struct c 1; struct c 1 { struct Example: talk 10. td // // struct c 1; struct c 1 { struct c 1 *list; }; // struct c 2 { // struct c 2 *list; // }; // used for subregisters class c 1; class c 1 param = []> { list l = param; } class c 2 param = []> { list l = param; } 20 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 11. td // // class Instruction<string n> { string variant = n; Example: talk 11. td // // class Instruction { string variant = n; } multiclass basic_r { def rr: Instruction< "rr">; def rm: Instruction<"rm">; } defm ADD : basic_r; defm SUB : basic_r; 21 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 11. td (output) ------- Classes --------class Instruction<string Instruction: n = ? > Example: talk 11. td (output) ------- Classes --------class Instruction { string variant = Instruction: n; string NAME = ? ; } ------- Defs --------def ADDrm { // Instruction rm string variant = "rm"; string NAME = ? ; } def ADDrr { // Instruction rr string variant = "rr"; string NAME = ? ; } 22 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 11. td (output) def SUBrm { // Instruction rm string variant = Example: talk 11. td (output) def SUBrm { // Instruction rm string variant = "rm"; string NAME = ? ; } def SUBrr { // Instruction rr string variant = "rr"; string NAME = ? ; } 23 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 12. td class Instruction<string n> { string variant = n; } multiclass Example: talk 12. td class Instruction { string variant = n; } multiclass basic_r { def rr: Instruction< "rr">; def rm: Instruction<"rm">; } multiclass basic_s { defm SS : basic_r; defm SD : basic_r; } defm ADD 2 : basic_s; 24 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 12. td (output) ------- Classes --------class Instruction<string Instruction: n = ? > Example: talk 12. td (output) ------- Classes --------class Instruction { string variant = Instruction: n; string NAME = ? ; } ------- Defs --------def ADD 2 SDrm { // Instruction rm SDrm string variant = "rm"; string NAME = ? ; } 25 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: talk 12. td (output) def ADD 2 SDrr { // Instruction rr SDrr Example: talk 12. td (output) def ADD 2 SDrr { // Instruction rr SDrr string variant = "rr"; string NAME = ? ; } def ADD 2 SSrm { // Instruction rm SSrm string variant = "rm"; string NAME = ? ; } def ADD 2 SSrr { // Instruction rr SSrr string variant = "rr"; string NAME = ? ; } 26 © 2011 MIPS Technologies, Inc. All rights reserved.

Understanding Register Definitions * Examples of Register Classes Intel 64 bit integer, 32 bit Understanding Register Definitions * Examples of Register Classes Intel 64 bit integer, 32 bit integer, 16 bit integer, 8 bit integer MIPS 64 bit integer, 32 bit float, 64 bit float In some cases, registers are aliased. Intel AX register consists of AH and AL MIPS 64 bit float contains a 32 bit sp even and 32 bit sp odd register Want to be able to refer to the various register pieces. Introduce notion of "subreg index". Subreg index is way to refer to the pieces. • Intel 16 bit registers contain two 8 bit integer registers, designated as Lo and Hi, this Ax containt AH and AL. • MIPS D 0 contains registers F 0, F 1 27 © 2011 MIPS Technologies, Inc. All rights reserved.

What About sub-registers? Given an x 86 16 -bit register, one identifies that AH What About sub-registers? Given an x 86 16 -bit register, one identifies that AH and AL are subregisters and will be in a list of subregisters. But how do you find the 8 bit low and 8 bit hi? Well there is a Parallel list of subregister indices to the list of subregisters. for example, in the AX register definition there will be. [AL, AH] [8 bit_lo, 8 bit] This could also be written [AH, AL] [8 bit, 8 bit_lo] 28 © 2011 MIPS Technologies, Inc. All rights reserved.

What About sub-registers? (cont. ) for MIPS D 0, the definition for subregisters would What About sub-registers? (cont. ) for MIPS D 0, the definition for subregisters would contain: [F 0, F 1] [FP_EVEN, FP_ODD] This could also be written [F 1, F 0] [FP_ODD, FP_EVEN] So then to find the 8 bit_lo subregister of AX, you search for AL in the subreg iindex list and take that index number and then find the parallel member of the subregister list. 29 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: from talk 15. td // From Target. td // Sub. Reg. Index - Example: from talk 15. td // From Target. td // Sub. Reg. Index - Use instances of Sub. Reg. Index to identify subregisters. class Sub. Reg. Index comps = []> { string Namespace = ""; // Composed. Of - A list of two Sub. Reg. Index instances, [A, B]. // This indicates that this Sub. Reg. Index is the result of composing A and B. list Composed. Of = comps; } // abbreviated Register. Class definition // class Register { string Asm. Name = n; list Sub. Regs = []; list Sub. Reg. Indices = []; } 30 © 2011 MIPS Technologies, Inc. All rights reserved.

Example: from talk 15. td class Register. With. Sub. Regs<string n, list<Register> subregs> : Example: from talk 15. td class Register. With. Sub. Regs subregs> : Register { let Sub. Regs = subregs; } // from X 86 Register. Info. td // def sub_8 bit : Sub. Reg. Index; // no subregisters def sub_8 bit_hi: Sub. Reg. Index; def AL : Register<"al">; def AH : Register<"ah">; let Sub. Reg. Indices = [sub_8 bit, sub_8 bit_hi] in { def AX : Register. With. Sub. Regs<"ax", [AL, AH]>; } 31 © 2011 MIPS Technologies, Inc. All rights reserved.

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