Скачать презентацию T 2 K electronics My understanding some gaps Скачать презентацию T 2 K electronics My understanding some gaps

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T 2 K electronics My understanding (some gaps) Beam structure ~ 3. 5 seconds T 2 K electronics My understanding (some gaps) Beam structure ~ 3. 5 seconds ~ 8 (9? ) bunches / spill bunch width ~ 60 nsec bunch separation ~ 600 nsec spill duration ~ 5 msec Time between spills ~ 3. 5 secs. Detector parameters (scintillator calorimeter) ~ 50, 000 channels (50 k Si. PMs) 1 event / bunch + cosmics (100 Hz) Electronics (physics) requirements event time: resolution ~ ns signal size: resolution? (no. of ADC bits? ) dynamic range? (few 100 p. C I think? ) linearity? noise? MR (7/7/05)

Trip chip ref. : Mc. Farland_MINERv. A_Electronics. pdf (presentation at Rome T 2 K Trip chip ref. : Mc. Farland_MINERv. A_Electronics. pdf (presentation at Rome T 2 K meeting, 6/12/04) discusses possible use of Trip (not Trip-t) ASIC in T 2 K Trip-t is newer version of Trip (we would be more likely to use Trip-t but this talk still has some interesting info) - generally positive, and gives estimates for front end costs ~ $440 k for 30 k channel system + $100 k LV distribution + $100 k DAQ Trip ASIC (32 channels – packaged chip) integrate charge over spill (or bucket), variable preamp gain up to 4 p. C dynamic range 48 stage pipeline stores analogue samples fast discriminator output -> FPGA -> timing in 5 nsec steps (could possibly do better) FPGA then passes pipeline trigger back to Trip 32 analogue samples muxed out to commercial ADC (12 -bit) MR (7/7/05)

Trip-t chip ref. : TRIP_t_Apr 05. ppt (Bellantoni – D 0 AFEII Director’s Review, Trip-t chip ref. : TRIP_t_Apr 05. ppt (Bellantoni – D 0 AFEII Director’s Review, 13/4/05) summarises measured performance of Trip-t & spec. improvements for 2 nd version (in fab now I think) Trip-t ASIC (32 channels - packaged) integrate charge over spill (or bucket), variable preamp gain up to 3 p. C dynamic range 48 stage pipeline stores analogue samples –> A pulse (7 bit precision) noise < 1 f. C (not sure whether this gain range dependent) time between disc. firing (any channel) and end of integration period -> t pulse (~ 2 nsec res’n) t pulse also stored in 48 stage pipeline disc. outputs read out during reset period -> FPGA -> pipeline trigger to Trip-t 32 A samples and 32 t samples muxed out to commercial ADCs power < 10 m. W/channel Is above spec. adequate for T 2 K application? MR (7/7/05)

Mc. Farland_MINERv. A_Electronics. pdf MR (7/7/05) Mc. Farland_MINERv. A_Electronics. pdf MR (7/7/05)

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TRIP_t_Apr 05. ppt MR (7/7/05) TRIP_t_Apr 05. ppt MR (7/7/05)

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possible new FE chip architecture fast preamp Si. PM disc. front end chip front possible new FE chip architecture fast preamp Si. PM disc. front end chip front end digital (FPGA based) thresh HV trim slow amp pk. hold functionality fast time stamp (~ns) Si. PM HV trim combine disc. O/Ps and generate address of channel that fired pk. hold e. g. 16 channels fast timing signal 4 bit add. control digitization of channel that fired assemble data packet and transmit (channel address, time stamp, ADC value) slow control set up HV trim, channel gains, thresholds, … would expect one FE FPGA to deal with more than one FE chip (maybe 8? ) Si. PM HV trim n bits pk. hold nothing “particularly” difficult here fast time stamping performed off-chip MR (7/7/05) ADC control ~ 20 lines

Idea to keep very fast functionality off FPGA good idea from Matt Noy deserializer Idea to keep very fast functionality off FPGA good idea from Matt Noy deserializer chip e. g. DS 90 CR 486 fast discriminator O/P from FE chip whichever line shows discriminator output first -> timing at 1/6 th of 133 MHz period (1. 25 nsec. ) 800 MHz PLL 133 MHz only DS 90 CR 486 -> 8 channels of 1: 6 deserialization (8: 48) => 1 chip for 8 FE chips 900 m. W power => 7 m. W / FE channel MR (7/7/05) FE FPGA

Chip count 16 Si. PMs 16 channel FE chip 16 Si. PMs 16 channel Chip count 16 Si. PMs 16 channel FE chip 16 Si. PMs 16 channel FE chip FE FPGA 16 channel FE chip 50, 000 channels 50, 000 Si. PMs 3125 FE chips (assume 16 channels) (maybe 390 deserializers) 390 FE FPGAs 16 channel FE MR (7/7/05) chip 16 Si. PMs FE FPGA 390 readout lines off-detector (or could combine) FE FPGA

Trip-t chip / new chip – a few pros and cons Trip-t chip Pros Trip-t chip / new chip – a few pros and cons Trip-t chip Pros No FE chip development required no development cost – just buy chips May be able to utilise other parts of Trip-t readout system? (or at least follow same approach) Trip-t chip Cons possible signal size incompatibility few p. C, we need few 100 p. C unless lower gain on Si. PM (maybe could just attenuate? ) no HV trim (may be possible to provide with commercial components) time resolution performance not good (but should be better for next version) more complicated functionality than necessary for T 2 K (e. g. pipeline) New chip Pros FE specification and functionality can be tailored to Si. PM New chip Cons development cost risk everything under our control MR (7/7/05)