Striplets option for SVT Layer 0 G Rizzo

Striplets option for SVT Layer 0 G. Rizzo for the Pisa Group Super. B Detector Meeting, Dec. 12 2006 G. Rizzo Super. B Det. Meeting 12/12/2006 1

In the last weeks • New inputs from background simulation indicate higher values w. r. t Nov. Workshop (see Paoloni’s talk 11/28). • Work on the striplets option for SVT Layer 0 with the following constraints: – – Layer_0 radius >= 1. 2 cm Occupancy <= 10% Reasonable number of readout channels Radiation damage issue • Layer 0 baseline design with a good candidate as front end chip (FSSR 2 developed for BTe. V) • Expected S/N • Rough estimate of material budget • Still to finalize mechanical details of the modules • Redo Pravda simulation on specific channels with this baseline configuration G. Rizzo Super. B Det. Meeting 12/12/2006 2

Layer 0 baseline design • Octagonal shape with R=1. 5 cm, LAB accept. 300 mrad in FW and BW • • Module active area = 1. 29 x 9. 7 cm 2 Double sided detector, 200 um thick, with striplets, (45 degrees w. r. t det edges), readout pitch 50 um. strip area = 50 um x 1. 83 cm, 3080 strips/module 770 strips readout on each short side of the module (left/right) – bring signals outside the active region with traces on a fanout support (as in SVT modules, z side several fanout layers/module depending on pitch Readout Left r= 1. 5 cm V U 1. 29 cm 9. 7 cm G. Rizzo Super. B Det. Meeting 12/12/2006 Readout Right 3

P side d~ 1. 29 cm L_strip ~ 1. 83 cm 50 mm L~ 9. 7 cm N side 50 mm Pstop to insulate n+ strips or pspray G. Rizzo Super. B Det. Meeting 12/12/2006 4

Front end chip I • Expected background hit rate = 5 MHz/cm 2 @ r=1. 5 cm – Including x 10 safety factor 50 MHz/cm 2 used in the following • L 0 strip rates (> 450 k. Hz) are not acceptable with present SVT front end (ATOM chip) : – With 1 ms readout window L 0 strip occupancy > 45% – Inefficiency due to shadowing: a single hit (the first in the readout window) is retrieved from the pipeline when LV 1 trigger is received background hits can shadow hits from physics – Such a high occupancy affects pattern recognition G. Rizzo Super. B Det. Meeting 12/12/2006 5

Front end chip II • Try a different approach for readout: fast, data driven readout architecture, with no analog storage, with enough output bandwidth to ensure that no data is lost due to readout deadtime. • FSSR 2, designed for the BTe. V Forward Silicon Tracker (Pavia/Bergamo-Fermilab), has the right features: – – TSMC 0. 25 µm CMOS tech. with enclosed NMOS Rad. Hard – 128 analog channels, sparsified digital output with address, timestamp, and pulse height information for all hits – – Mixed-signal integrated circuit for the readout of silicon strip detectors (selectable shaper peaking time: 65 -85 -125 ns) Architecture designed to run with 132 ns bunch crossing (timestamp granularity = BCO clock = 7. 6 MHz), readout clock @ 70 MHz 840 Mb/s output data rate. For more details on FSSR 2 see for example: • V. Re et al. , “FSSR 2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors”, 2005 IEEE Nuclear Science Symposium Conference Record • V. Re: “First prototype of a silicon microstrip detector with the data-driven readout chip FSSR 2 for a tracking-based trigger system” , presented @ 10 th Pisa Meeting on Advanced Detectors, La Biodola (Isola d’Elba), May. Super. B Det. Meeting 12/12/2006 21 – 27, 2006 G. Rizzo 6

FSSR 2 for L 0 striplets • In Super. B L 0 expected FSSR 2 chip occupancy (132 ns) = 6% – Should be OK for pattern recognition – Is FSSR 2 fast enough for Super. B? – YES, if you believe to simulation performed for BTe. V • FSSR 2 chip optimized for BTe. V operation: – With 2 interactions/bunch crossing (132 ns), expected BTe. V FSSR 2 occupancy 2% – With standard operation (132 ns BCO clock) FSSR 2 can handle 2% occupancy with efficiency > 99%. • FSSR 2 Simulation performed for BTe. V with 6% occupancy (6 interactions/bunch crossing) indicates: – Efficiency ~ 96. 5%, with standard BCO clock frequency – Can improve efficiency (~ 98. 5%) with x 4 BCO clock frequency. • FSSR 2 chip can read L 0 striplets (6% occupancy) with 98. 5% efficiency G. Rizzo Super. B Det. Meeting 12/12/2006 7

FSSR Efficiency Verilog Simulation (Jim Hoff - Fermilab) Green and light blue lines corresponds to performance with 65 ns peaking time Improve efficiency with x 4 BCO clock frequency (30 MHz) = Occupancy (%) G. Rizzo Super. B Det. Meeting 12/12/2006 8

Expected S/N with FSSR 2 G. Rizzo Super. B Det. Meeting 12/12/2006 9

Detector capacitance • Contribution to total capacitance from Si detector and fanout: – Interstrip – Back plane Pitch mm width mm d mm L strip Cm e_eq CIS p. F/cm Cback p. F/cm C pf Si det 50 28 200 1. 83 7. 6 1. 85 0. 26 3. 85 fanout 50 20 50 Upilex +35 air 10 2. 2 0. 44 0. 09 5. 31 • Total det capacitance ~ 9 p. F G. Rizzo Super. B Det. Meeting 12/12/2006 10

CIS//2 fanout Cback CIS//2 air Si det G. Rizzo Cback Super. B Det. Meeting 12/12/2006 11

Layer 0 S/N with FSSR 2 • Assume noise performance as measured in FSSR 2: – ENC=a+b*CD – a=240 e- , b=35 e-/p. F • Serie resistance increases by ~ 14% the slope b: FSSR 2 noise vs det Capacitance CD = 9 p. F Rs = Lfanout *2 /cm + Ldet*20 /cm=55 e_n=4 k. T Rs/3 Equivalent Noise Charge = 600 e- • Signal = 16000 e- (Si 200 um thick) • S/N = 26 ( ~ 24 including 300 e- thr. dispersion added to noise in quadrature) G. Rizzo Super. B Det. Meeting 12/12/2006 12

Layer 0 material budget • Layer 0 average thickness 0. 46% X 0 – Silicon detector 200 um – Support structure ~ 100 um Si eq. – ~3 fanout layers/module ~ 135 um Si eq. • How many fanout layers/module are needed? • Using Aluminum microcables, as used in Alice Si modules, we could reduce the material (10 um Si eq/layer) and simplify the assembly (Tape Automated Bonding) • need to understand if 50 um pitch is possible • Layer 0 average thickness could be ~ 0. 35 % X 0 ( 330 um Si eq. ) G. Rizzo Super. B Det. Meeting 12/12/2006 • Readout channels ~ 3080/module, 770 strips readout on each short side of the module (see next slide). • several fanout layers/module needed, depending on pitch and on aspect ratio (dimensions of the short side) • Assuming 50 um pitch and using a lateral extension, on the short side of the detector, for fanout strip routing (dtot=2*1. 29 cm) one needs about 1. 5 fanout layers/view 3 fanout layers/module (~ 45 um Si eq/fanout) 13

…just to give you an idea of a module… Readout Left Readout Right Si detector 1 st fanout, 2 nd fanout HDI L 0 r-f cross section at |z|>5 cm (outside the active region) CAD design in progress Fanout estension z HDI Si det R = 1. 5 cm G. Rizzo Super. B Det. Meeting 12/12/2006 14

Radiation Hardness • Si detector dose ~ 6. 6 Mrad/yr (safety included). Should be ok (rough estimate of noise contribution due to leakage current ~ 670 e- after 5 years of operation, to be added in quadrature to previous noise figure). • Chip dose depends on their radial location. – Assuming chip located at radius of ~ 2. 4 cm expected chip dose ~ 200 krad/yr OK ! FSSR 2 < Irradiation with 60 Co g-rays to a total ionizing dose of 20 Mrad (no bias applied during irradiation) < Chip fully functional after irradiation; noise and charge sensitivity are not affected < Threshold dispersion with BLR selected increases by about 15 % (remains below the spec value of 500 e rms) G. Rizzo Super. B Det. Meeting 12/12/2006 15

Backup G. Rizzo Super. B Det. Meeting 12/12/2006 16

A Layer 0 module Readout Left Readout Right Si detector 1 st fanout, 2 nd fanout HDI z G. Rizzo Super. B Det. Meeting 12/12/2006 17

Ba. Bar SVT L 1 module G. Rizzo Super. B Det. Meeting 12/12/2006 18

Fanout estension HDI Si det G. Rizzo Super. B Det. Meeting 12/12/2006 19

G. Rizzo Super. B Det. Meeting 12/12/2006 20