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Hardware and Petri nets Synthesis of asynchronous circuits from Signal Transition Graphs Hardware and Petri nets Synthesis of asynchronous circuits from Signal Transition Graphs

Outline • • Overview of the synthesis flow Specification State graph and next-state functions Outline • • Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Speed-independent circuit Logic decomposition

Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

x y x z y z z+ x+ xy+ z- y. Signal Transition Graph x y x z y z z+ x+ xy+ z- y. Signal Transition Graph (STG)

x y z z+ x+ xy+ y- z- x y z z+ x+ xy+ y- z-

xyz 000 x+ z+ xy+ y- z- y- x- 001 y+ 100 y+ 101 xyz 000 x+ z+ xy+ y- z- y- x- 001 y+ 100 y+ 101 110 y+ z+ 011 z- 010 111 x-

xyz 000 Next-state functions x+ z+ y- x- 001 y+ 100 y+ 101 110 xyz 000 Next-state functions x+ z+ y- x- 001 y+ 100 y+ 101 110 y+ z+ 011 z- 010 111 x-

Next-state functions x y z Next-state functions x y z

Simple examples A+ B+ AB- A B A input B output Simple examples A+ B+ AB- A B A input B output

Simple examples A+ B+ A AB- B Simple examples A+ B+ A AB- B

Simple examples A+ BA AB+ B Simple examples A+ BA AB+ B

Simple examples A+ B+ A C+ C A- BC- B C Simple examples A+ B+ A C+ C A- BC- B C

Simple examples A+ B+ C+ ABC- A C B C Simple examples A+ B+ C+ ABC- A C B C

A FIFO controller Ri+ Ro FIFO cntrl Ao Ai Ao+ Ai+ Ri- Ro- Ao- A FIFO controller Ri+ Ro FIFO cntrl Ao Ai Ao+ Ai+ Ri- Ro- Ao- Ri Ro+ Ai- Ri Ao C C Ro Ai

Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

VME bus Bus DSr Data Transceiver LDS Device D DSr DSw LDS VME Bus VME bus Bus DSr Data Transceiver LDS Device D DSr DSw LDS VME Bus Controller LDTACK D DTACK Read Cycle

STG for the READ cycle DSr+ LDS+ LDTACK+ DTACK- D+ DTACK+ LDTACK- LDS- D STG for the READ cycle DSr+ LDS+ LDTACK+ DTACK- D+ DTACK+ LDTACK- LDS- D DSr DTACK VME Bus Controller LDS LDTACK DSr- D-

Choice: Read and Write cycles DSr+ LDS+ D+ LDTACK- DSw+ LDS+ D+ DTACK- LDTACK+ Choice: Read and Write cycles DSr+ LDS+ D+ LDTACK- DSw+ LDS+ D+ DTACK- LDTACK+ LDS- D- DSr- DTACK+ D- DSw- LDTACK- LDS-

Choice: Read and Write cycles DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ D+ DTACK+ LDTACKLDS- Choice: Read and Write cycles DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ D+ DTACK+ LDTACKLDS- DTACK- LDTACK+ D- DSr- DTACK+ D- DSw-

Circuit synthesis • Goal: – Derive a hazard-free circuit under a given delay model Circuit synthesis • Goal: – Derive a hazard-free circuit under a given delay model and mode of operation

Speed independence • Delay model – Unbounded gate / environment delays – Certain wire Speed independence • Delay model – Unbounded gate / environment delays – Certain wire delays shorter than certain paths in the circuit • Conditions for implementability: – Consistency – Complete State Coding – Persistency

Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

STG for the READ cycle DSr+ LDS+ LDTACK+ DTACK- D+ DTACK+ LDTACK- LDS- D STG for the READ cycle DSr+ LDS+ LDTACK+ DTACK- D+ DTACK+ LDTACK- LDS- D DSr DTACK VME Bus Controller LDS LDTACK DSr- D-

Binary encoding of signals DSr+ LDS+ LDTACKDSr+ LDS- LDTACK+ DSr+ D+ DTACK- LDTACKLDS- DTACK- Binary encoding of signals DSr+ LDS+ LDTACKDSr+ LDS- LDTACK+ DSr+ D+ DTACK- LDTACKLDS- DTACK- DDTACK+ DSr- LDTACK-

Binary encoding of signals DSr+ 10000 LDS+ LDTACK- DSr+ 10010 LDS- LDTACK+ DTACKLDS- DSr+ Binary encoding of signals DSr+ 10000 LDS+ LDTACK- DSr+ 10010 LDS- LDTACK+ DTACKLDS- DSr+ 10110 D+ DTACK- LDTACK- 01100 LDS- DTACK- 01110 00110 10110 DDTACK+ DSr- (DSr , DTACK , LDS , D)

Excitation / Quiescent Regions ER (LDS+) LDS+ QR (LDS-) LDS- QR (LDS+) LDS- ER Excitation / Quiescent Regions ER (LDS+) LDS+ QR (LDS-) LDS- QR (LDS+) LDS- ER (LDS-)

Next-state function 0 1 LDS+ 1 1 10110 0 0 LDS- 1 0 10110 Next-state function 0 1 LDS+ 1 1 10110 0 0 LDS- 1 0 10110

Karnaugh map for LDS = 1 LDS = 0 D LDTACK DSr 00 01 Karnaugh map for LDS = 1 LDS = 0 D LDTACK DSr 00 01 11 10 00 0 0 - 1 00 - - - 1 01 - - - - 11 - 1 10 0 0 - 0/1?

Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

Concurrency reduction DSr+ LDS+ DSr+ LDSDSr+ 10110 LDS- Concurrency reduction DSr+ LDS+ DSr+ LDSDSr+ 10110 LDS-

Concurrency reduction DSr+ LDS+ LDTACK+ D+ LDTACK- DTACK+ LDS- DSr- D- Concurrency reduction DSr+ LDS+ LDTACK+ D+ LDTACK- DTACK+ LDS- DSr- D-

State encoding conflicts LDS+ LDTACK- LDS- 10110 State encoding conflicts LDS+ LDTACK- LDS- 10110

Signal Insertion CSC+ LDS+ LDTACK- LDS- 101101 101100 D- DSr- CSC- Signal Insertion CSC+ LDS+ LDTACK- LDS- 101101 101100 D- DSr- CSC-

Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

Complex-gate implementation Complex-gate implementation

Implementability conditions • Consistency – Rising and falling transitions of each signal alternate in Implementability conditions • Consistency – Rising and falling transitions of each signal alternate in any trace • Complete state coding (CSC) – Next-state functions correctly defined • Persistency – No event can be disabled by another event (unless they are both inputs)

Implementability conditions • Consistency + CSC + persistency • There exists a speed-independent circuit Implementability conditions • Consistency + CSC + persistency • There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that ay Boolean function can be implemented with one complex gate)

Persistency 100 a- 000 c+ 001 b+ b+ a c b is this a Persistency 100 a- 000 c+ 001 b+ b+ a c b is this a pulse ? Speed independence glitch-free output behavior under any delay

a+ 0000 a+ b+ 1000 b+ 1100 a- a- 0100 c+ c+ 0110 d+ a+ 0000 a+ b+ 1000 b+ 1100 a- a- 0100 c+ c+ 0110 d+ d+ 0111 a+ a+ 1111 b- ba- 1011 cd- a- 0011 c- a- c- 1001 0001 d-

cd ab 00 01 11 00 0 01 0 11 0 a+ 1000 0 cd ab 00 01 11 00 0 01 0 11 0 a+ 1000 0 b+ 1100 1 0000 10 1 1 1 a- 0100 ER(d+) c+ 0110 d+ 10 0111 1 a+ 1111 b- 1011 a- 0011 ER(d-) c- a- c- 1001 0001 d-

cd ab 00 01 11 00 0 01 0 11 0 0 1 10 cd ab 00 01 11 00 0 01 0 11 0 0 1 10 1 1 1 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d+ 10 1 0111 a+ 1111 b- 1011 a- 0011 Complex gate c- a- c- 1001 0001 d-

Implementation with C elements S R C z • • • S+ z+ S- Implementation with C elements S R C z • • • S+ z+ S- R+ z- R- • • S (set) and R (reset) must be mutually exclusive • S must cover ER(z+) and must not intersect ER(z-) QR(z-) • R must cover ER(z-) and must not intersect ER(z+) QR(z+)

cd ab 00 01 11 00 0 01 0 11 0 a+ 1000 0 cd ab 00 01 11 00 0 01 0 11 0 a+ 1000 0 b+ 1100 1 0000 10 1 a- 0100 c+ 1 1 0110 d+ 10 0111 1 a+ 1111 b- 1011 S R C d a- 0011 c- a- c- 1001 0001 d-

0000 a+ 1000 b+ 1100 but. . . a- 0100 c+ 0110 d+ 0111 0000 a+ 1000 b+ 1100 but. . . a- 0100 c+ 0110 d+ 0111 a+ 1111 b- 1011 S R C d a- 0011 c- a- c- 1001 0001 d-

Assume that R=ac has an unbounded delay Starting from state 0000 (R=1 and S=0): Assume that R=ac has an unbounded delay Starting from state 0000 (R=1 and S=0): 0000 a+ 1000 b+ 1100 a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; a- 0100 c+ R+ disabled (potential glitch) 0110 d+ 0111 a+ 1111 b- 1011 S R C d a- 0011 c- a- c- 1001 0001 d-

cd ab 00 01 11 00 0 01 0 11 0 a+ 1000 0 cd ab 00 01 11 00 0 01 0 11 0 a+ 1000 0 b+ 1100 1 0000 10 1 a- 0100 c+ 1 1 0110 d+ 10 0111 1 a+ 1111 b- 1011 S R C d a- 0011 c- a- 1001 0001 Monotonic covers c- d-

C-based implementations S R c a b c d C C b a d C-based implementations S R c a b c d C C b a d weak d c a generalized C elements (g. C) weak d

Speed-independent implementations • Implementability conditions – Consistency – Complete state coding – Persistency • Speed-independent implementations • Implementability conditions – Consistency – Complete state coding – Persistency • Circuit architectures – Complex (hazard-free) gates – C elements with monotonic covers –. . .

Synthesis exercise y- 1001 z- zy+ wx+ z+ w+ x- y+ 1010 1000 w- Synthesis exercise y- 1001 z- zy+ wx+ z+ w+ x- y+ 1010 1000 w- w- z- w- y+ 0010 y- 0000 x+ w+ 0101 x+ z- 0011 0100 x- x+ y+ 0110 0001 1011 z+ 0111 Derive circuits for signals x and z (complex gates and monotonic covers)

Synthesis exercise yz wx 1001 z 00 01 11 10 00 1 1 - Synthesis exercise yz wx 1001 z 00 01 11 10 00 1 1 - 0 y+ 01 1 1 - 0 1010 11 0 0 - 0 10 1 1 - 0 Signal x 1000 w- w- z- w- y+ 0010 y- 0000 x+ w+ 0101 x+ z- 0011 0100 x- x+ y+ 0110 0001 1011 z+ 0111

Synthesis exercise yz wx 1001 z 00 01 11 10 00 0 0 - Synthesis exercise yz wx 1001 z 00 01 11 10 00 0 0 - 0 y+ 01 0 0 - 0 1010 11 1 1 - 1 10 0 1 - 0 Signal z 1000 w- w- z- w- y+ 0010 y- 0000 x+ w+ 0101 x+ z- 0011 0100 x- x+ y+ 0110 0001 1011 z+ 0111

Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean Specification (STG) Reachability analysis State Graph State encoding Design flow SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

No Hazards abcx 1000 b+ 1100 a 0100 c+ 0110 11 0 0 01 No Hazards abcx 1000 b+ 1100 a 0100 c+ 0110 11 0 0 01 1 1 00 0 1 a b c x 0

Decomposition May Lead to Hazards abcx 1000 b+ 1100 a 0100 c+ 0110 111000 Decomposition May Lead to Hazards abcx 1000 b+ 1100 a 0100 c+ 0110 111000 011111 a b 001110 z 000011 c x 000010

Global acknowledgement d- b+ d+ y+ a- y- c+ d- c- d+ z- b- Global acknowledgement d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- c b a z a b d y

How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- c b a z a b d y

How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- c z b a a b d y

How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- c 0 b a a b d 0 z y

How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- a c b a z y b d

How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- How about 2 -input gates ? d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- c z a b y d

Strategy for logic decomposition • Each decomposition defines a new internal signal • Method: Strategy for logic decomposition • Each decomposition defines a new internal signal • Method: Insert new internal signals such that – After resynthesis, some large gates are decomposed – The new specification is hazard-free • Generate candidates for decomposition using standard logic factorization techniques: – Algebraic factorization – Boolean factorization (boolean relations)

Signal insertion for function F Insertion by input borders F+ F=0 F=1 FState Graph Signal insertion for function F Insertion by input borders F+ F=0 F=1 FState Graph

Event insertion a b ER(x) c Event insertion a b ER(x) c

Event insertion SR(x) a a b x x x b ER(x) x c Event insertion SR(x) a a b x x x b ER(x) x c

Properties to preserve a b a b a a is disabled by b = Properties to preserve a b a b a a is disabled by b = hazards b x x a b a is persistent a b b x a

Decomposition example 1001 zy+ 1010 1000 w- w- z- w- y+ 0010 y- 0000 Decomposition example 1001 zy+ 1010 1000 w- w- z- w- y+ 0010 y- 0000 x+ 1011 w+ 0101 x+ z- 0011 0100 x- x+ y+ 0110 0001 z+ y- 0111 z- w- w+ y+ x+ x- z+

1001 zy+ 1010 1000 w- w- z- w- y+ 0010 y- 0000 yz=0 x+ 1001 zy+ 1010 1000 w- w- z- w- y+ 0010 y- 0000 yz=0 x+ 1011 0100 x- z+ 0111 yz=1 w y z w+ 0101 x+ z- x+ y+ 0110 0001 x y z x w w z x y z y C z

s=1 zy+ 1010 1000 s- y+ 1010 1001 s=0 y- 1011 s 1001 s- s=1 zy+ 1010 1000 s- y+ 1010 1001 s=0 y- 1011 s 1001 s- z 1000 0001 x+ 0100 z+ x- 0111 x w w z 0111 s+ w s y z 0011 0101 x+ z- x+ y+ 0110 w+ w- w- z- w- y+ 0010 x x y z y C z

s=1 zy+ 1010 1000 s- y+ 1010 1001 s=0 1001 1000 w- y+ 0000 s=1 zy+ 1010 1000 s- y+ 1010 1001 s=0 1001 1000 w- y+ 0000 0110 0001 0011 x+ 0101 x+ z- x+ y+ s- w+ w- w- z- y- 1011 s- s- z- 0010 y- 0100 z+ z- w- w+ y+ x+ x- x 0111 s+ 0111 z+ s+

zy+ 1010 1001 1000 w- w- z- w- y+ 0010 y- 0000 yz=0 x+ zy+ 1010 1001 1000 w- w- z- w- y+ 0010 y- 0000 yz=0 x+ 0101 x+ z- x+ y+ 0110 0001 0100 z+ x y z 1011 w y z w+ x w 0011 w z x 0111 yz=1 x y z y C z

s=1 1001 s 1001 zy+ 1010 1000 w- y+ 0010 s=0 0110 s- w+ s=1 1001 s 1001 zy+ 1010 1000 w- y+ 0010 s=0 0110 s- w+ 0001 0011 x+ 0101 x+ z- x+ y+ y- 1011 w- w- z 0000 y- 0100 z+ z- w- w+ y+ x+ x- x 0111 s+ 0111 z+ z- is delayed by the new transition s- ! s+

x zy+ 1010 1001 1000 w- w- z- w- y+ 0010 y- 0000 0110 x zy+ 1010 1001 1000 w- w- z- w- y+ 0010 y- 0000 0110 yz=0 y z 0001 x+ 0101 x+ z- x+ y+ 1011 w 0100 z+ w+ x w 0011 w z x 0111 yz=1 y x y z C y C z

Conclusions • The synthesis of asynchronous control circuits from Petri net specifications can be Conclusions • The synthesis of asynchronous control circuits from Petri net specifications can be totally automated • Existing tools at academia (http: //www. lsi. upc. es/~jordic/petrify) • An asynchronous circuit is a concurrent system with processes (gates) and communication (wires) • The theory of concurrency is crucial to formalize automatic synthesis methods