Скачать презентацию SKADS and SKA Andrew Faulkner 4 th SKADS Скачать презентацию SKADS and SKA Andrew Faulkner 4 th SKADS

94e7e698ded43ceddbd0b926e7a33d66.ppt

  • Количество слайдов: 17

SKADS and SKA Andrew Faulkner 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew SKADS and SKA Andrew Faulkner 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 1

Aperture Arrays are Important to the SKA Performance 4 th SKADS Workshop, Lisbon SKADS Aperture Arrays are Important to the SKA Performance 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 2

SKA Science Requirements AA AA AA 4 th SKADS Workshop, Lisbon SKADS and SKA SKA Science Requirements AA AA AA 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 3

SKA Memo 100 AA in all scenarios <500 MHz WBF+ Dense AA 4 th SKA Memo 100 AA in all scenarios <500 MHz WBF+ Dense AA 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 4

SKA Structure 0. 3 -1. 0 GHz Wide Fo. V Dense AA Digital Signal SKA Structure 0. 3 -1. 0 GHz Wide Fo. V Dense AA Digital Signal Processing . . . 70 -450 MHz Wide Fo. V . . Time Control Sparse AA Mass Storage . . . Correlator – AA & Dish 16 Tb/s . . . Data Central Processing Facility - CPF To 250 AA Stations Post Processor 0. 8 -10 GHz DSP 12 -15 m Dishes Control Processors & User interface 80 Gb/s DSP . . . To 2400 Dishes 4 th SKADS Workshop, Lisbon SKADS and SKA Time Standard User interface via Internet Andrew Faulkner 5

Demonstrator: EMBRACE 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 6 Demonstrator: EMBRACE 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 6

Demonstrator: 2 -PAD External Analogue only Clock distribution Mid-Plane Bunker wall Memory ADC PSU Demonstrator: 2 -PAD External Analogue only Clock distribution Mid-Plane Bunker wall Memory ADC PSU LNA Analog Cond. Backplane 10 Gb links I/F Board FPGA Digital Preprocessor Digital acquisition FPGA Antenna Array Coax Processing Rack Signal Conditioning Rack Cyclops Processor Beamforming processing Reg Memory FPGA Digital Preprocessor I/F Board Power supplies SKADS and SKA Cyclops Processor Power supplies Control System 4 th SKADS Workshop, Lisbon FPGA Cat-7 Distribution ADC PSU Gain & Drive HSS links Cooling Systems Andrew Faulkner 7

Demonstrator BEST 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 8 Demonstrator BEST 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 8

Challenges Cost: Technical: • Processing ability, power • Reducing Tsys requirements and cost • Challenges Cost: Technical: • Processing ability, power • Reducing Tsys requirements and cost • Limiting self-induced RFI • Digitisation implementation • Internal & external communication data cost • Ability to perform back-end processing • Mass manufacturing • Reducing systematics: …Dynamic Range! • Calibration methodology • Environmental: heat, bugs, lightening etc 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 9

Deliverables (just DS 3 and 4!) 4 th SKADS Workshop, Lisbon SKADS and SKA Deliverables (just DS 3 and 4!) 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 10

Deliverables (just DS 3 and 4!) d e t le p m o c Deliverables (just DS 3 and 4!) d e t le p m o c DS 3 -T 1 DS 4 -T 1 1. Report on COTS technology for data links 2. Report on component-based technology for data links 3. Prototype phase transfer links over various span lengths 4. Report on performance of phase transfer system over real installed fibre links 5. Report on prototype data links over short and long spans 6. Detailed cost models for COTS and component-based data applicable to various network and processing architectures 1. Establish benchmark LNA simulations to provide performance feedback for device process development 2. RF on wafer (RFOW) measurements on device wafers fabricated 3. Design, fabrication and testing of Si. Ge band pass filter using PIC Technology 4. LNA design techniques simulation study 5. ADC Design rule established and recommend ADC architectures 6. ADC building blocks design, fabrication and performance 7. Design, manufacture and test of hybrid LNA using novel discrete devices developed in programme (two iterations) 8. Fabricate and test Integrated ADC circuits 9. Fabricate and test of advanced integrated interconnect technologies with Si and Ga. As technologies. 10. Fabricate and test further LNA technologies – iterations 2 and 3 11. Fabricate and test further ADC technologies - iterations 2 and 3 12. Final report on different semiconductor technologies DS 3 -T 2 1. Processing architectural design documents 2. Software design documents 3. Cost and power usage evaluations for the various processing architectures 4. Cost evaluations for the software architecture 5. Technology assessment and road mapping overview reports DS 3 -T 3 1. Initial report on conceptual issues concerning the SKA network, data flow and processing 2. Delivery of functional simulator 3. Report on analysis of performance of the SKA using the simulator DS 3 -T 6 o t ll A DS 4 -T 2 e b DS 4 -T 6 1. Wide band, high dynamic range A/D blocks 2. Digital Down Converters 3. Sizing of the digital word at different levels of system 4. Low cost Poly-Phase filter banks 5. Data distribution and synchronization 6. A quasi-perfect reconstruction equi-spaced filter bank DS 4 -T 3 1. Develop RFI mitigation strategies for the phased-array concept of SKA, at a station level and for the instrument as a whole; 2. Assess the influence of these methods on data quality; 3. Assess the cost effectiveness of these methods for the RFI environment of the selected SKA site; 4. Demonstrate practical RFI mitigation techniques for the EMBRACE and BEST SKADS demonstrators DS 4 -T 4 1. Wide band integrated antenna, dual polarization 2. Low cost antenna technology 3. Low cost packaging solutions 4. Low cost analogue photonic link 5. Reports on all of the above deliverables 6. Publications and Ph. D thesis DS 4 -T 5 1. Spec. of a prototype control and data processing system 1. Dual polarization all-digital tile 2. Specification and implementation of constructs, interfaces and components 2. Design documentation package for all-digital tile 3. Test environment for prototype all-digital tile. 3. Platform specific composition/deployment of control and data processing software for several alternative hardware platforms 2. Prototype of a lower cost analogue beam-former in Silicon (not in time for EMBRACE. ) 4. Evaluation report of tile performance. 3. Prototype digital beamformer for 2 -PAD. 5. Tile cost estimates projected for SKA volumes and timescales. 4. Architecture design for the whole digital beam-forming system for 2 -PAD. 6. Reliability analysis report. 5. A final report on the trade-offs and cost-effectiveness of analogue and digital beam-forming systems. 4. assessment of the readiness for scalabilit with MDA 5. rec. guideline for scalable design and implementation 4 th SKADS Workshop, Lisbon SKADS and SKA 1. Analogue beamformer in Ga. As for EMBRACE. Andrew Faulkner 11

Technology Readiness Levels 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 12 Technology Readiness Levels 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 12

Technology Readiness Levels SKA in operation SKA Phase 1 Target for AAVP Prep. SKA Technology Readiness Levels SKA in operation SKA Phase 1 Target for AAVP Prep. SKA & SKADS Mostly pre-SKADS work Full System Test & Operations System/Subsystem Development Technology Demonstration Technology Development Research to Prove Feasibility Basic Technology Research Ref: NASA http: //en. wikipedia. org/wiki/Technology_Readiness_Level 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 13

4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 14 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 14

System Group Purpose: Focussed advisory group to DS 8 to prepare final SKADS report System Group Purpose: Focussed advisory group to DS 8 to prepare final SKADS report Timing: Continue work from Design and Cost team Deliverable: Core report and ‘arguments’ for SKADS end March 2009 Starting: Autumn 2008 Discussion: With DS 8 team 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 15

System Group - Members Andrew Faulkner (Chair) Peter Wilkinson Steve Torchinsky Arnold van Ardenne System Group - Members Andrew Faulkner (Chair) Peter Wilkinson Steve Torchinsky Arnold van Ardenne Andre van Es Paul Alexander Dion Kant Stelio Montebugnoli Mike Jones Steve Rawlings Rosie Bolton Jan Geralt bij de Vaate 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 16

DS 8 Deliverables… 1. Scientific and technical specification for the SKA (T 0+47); 2. DS 8 Deliverables… 1. Scientific and technical specification for the SKA (T 0+47); 2. Overall System SKADS Design (T 0+48); Now the responsibity of “Final Deliverable” 3. Costing and budget assessment paying attention to the civil works Prep. SKA WP 6 required for the overall. This has been embodied in array to be included in the Preliminary SKA plan(T 0 to T 0+48); Memo #100. This memo or its SKA We arederivativeon the deliverable working is the SKA AA 4. Preliminary SKA plan including a study of funding sources scenario from SKA memo #100 (T 0+48); The cost modelling is in the System 5. Square Kilometre Array “White Paper” to be submitted to the International. Group remit. Committee, to work on to the SKA Steering We cannot the EC and national funding agencies whichcivil works to SKADS (T 0+48). budget or contributed 4 th SKADS Workshop, Lisbon SKADS and SKA Andrew Faulkner 17