Reliable Architecture for Flash Memory Amit Berman Joint work with Uri C. Weiser, Acknowledgement: thanks to Idit Keidar Department of Electrical Engineering, Technion – Israel Institute of Technology 1
Agenda Ø Reliability in Flash Memory Ø “Reliable Architecture” Ø The advantages of “Reliable Architecture” • Density • Performance Ø Conclusions 2
Introduction Ø Reliability: a crucial factor in flash memory design Ø Quantification: Guaranteed # of times that a memory cell can be written and erased before an error occurs • Basic physical characteristic of flash memory cell: every write/erase operation, the memory cell is degraded • Eventually, there would be a data error in the memory cell, proportional to the number of write/erase operations Our goal is to reduce the number of physical write/erase operations of the flash memory cells Analogy : Flash memory cell as a glass of water • The amount of water in the glass represents the information 3 Level - 1 • Each time we will fill and empty the glass – it will be cracked
Reliability is important for density Ø Good reliability high density Ø Bad reliability low density “fewer glass cracks, low water leakage” we can distinguish between more levels Full Level - 3 Level - 2 Level - 1 Empty Level- 0 4 1 Erased 0 Programmed : Bit : Level 2 bits per cell (2 BPC) # of cells 1 bit per cell (1 BPC) 11 10 01 0 1 2 00 : Bit 3 : Level Vt Vt Ref Increase density decrease reliability. Ref 2 Ref 3 Ref 1 Reliable Architecture technique increase the reliability We can use it to increase the density and keep constant reliability
Reliability is important for performance Ø Bad reliability low writing speed “glass cracks makes it hard to fill it” Ø Good reliability high writing speed Level - 2 # of cells Level- 0 Level - 0 11 10 01 0 1 2 00 : Bit 3 : Level # of cells Level - 0 Level- 0 11 10 01 0 1 2 Vt 5 Ref 1 Ref 2 Ref 3 00 : Bit 3 : Level Vt Ref 1 Ref 2 Ref 3
Related Work Ø Coding * M. Schwartz, S. Bruck “Rank Modulation for Flash Memories” Ø MFG Process * M. Yanai, I. Bloom “NROM memory cell design” 6
Observation Ø Flash data is erased in blocks (e. g. 64 KB) • The memory needs to be erased in order to write new information • Erase operation lasts long (e. g. 1. 5 m. S) cells are erased in groups erase Ø There are redundant write and erase operations erase write The cell returned to its original level 7
Observation: Example Ø There are redundant write and erase operations Time At time T 1, information is written Block is erased to enable new write New write is same as the initial value T 1 Vt T 2 Vt T 3 Vt In this process there are total 2 writes and 1 erase operations, can we reduce it to 1 write operation? 8
Reliable Architecture Ø New concept of operating flash memory Common Architecture vs. Reliable Architecture Write Erase Virtual Erase Read 9 Re-write (no change)
Re-write concept Flash Re-write Concept read the stored data, compare it to the input data and adjust for the difference if exists read and adjust If equal: do nothing If difference: adjust 10
Virtual erase concept Ø Construct a “spare memory array” that contain information about erase status Ø Virtual erase process: when erase is applied to a certain block/page Ø Mark a flag in the spare memory array for erase indication Ø Data is not physically erased erase virtual erase flag Analog HV Non-Volatile Memory Array Control Logic Spare NVM Valid Indication I/O 11
Reliable Architecture: changes to the current architecture ØTarget: Avoid redundant write and erase operations ØChanges: Arrange the memory array so that erase in a single cell is enabled Change the control logic for the new operations Add spare memory cells for virtual erase operation 12
Analysis : symmetric binary source While applying memory write, average # of cells with no transition: NT=# of bits with no transition l= # of flash memory levels n= # of bits in a page Average # of cells with write transition: Average # of cells with erase transition: 13
Example For 2 -levels flash with random input data source: ØEach writing operation 50% of the memory cells hold the same value 25% of the memory cells have write transition 25% of the memory cells have erase transition Saves 50% of write/erase operations, x 2 improvement * Taking into account Gaussian distribution 14
Reliability Improvement Factor (RIF) while using Reliable Architecture RIF is lower bound since we also save some transitions between levels 15
Performance analysis Ø Reliable architecture has advantage in large page size: Erase Operation ~1. 5 ms Erase can be done in parallel, for any # of memory cells Write Operation ~0. 8 ms Writing is done sequentially due to current consumption limitations (2 KB page) Ø The Reliable Architecture re-write concept uses the erase operation on some of the cells Ø On small page size, the erase transition reduce performance ØIn a large page size, the write performance is better then the one in common architecture 16
Performance analysis ØModeling results of flash memory cells, write and erase operations with varying page size, utilizing a symmetric data source *MATLAB Reliable Architecture is effective in large page size (>8 KB) 17
Summary Ø Reliable Architecture statistically improves flash memory reliability • Can be used to increase reliability • Can be use to increase density and keep reliability constant Ø Reliable Architecture improves reliability by the elimination of the redundant write/erase operations to the flash memory Ø Reliable Architecture is improving the write performance in page size >8 KB in a smaller page size, write performance is reduced 18
Questions? High Density Low $/MB ROM EPROM DRAM SRAM FLASH Nonvolatile 19 EEPROM Updateable
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