RAPIDSMITH DO-IT-YOURSELF CAD TOOLS FOR XILINX FPGAS Christopher

RAPIDSMITH: DO-IT-YOURSELF CAD TOOLS FOR XILINX FPGAS Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan Brent Nelson and Brad Hutchings FPL September 5 -7, 2011

Why Build Your Own Tools Anyway? • Proof of concept in their own right – Hypothetical architectures may not account for all real-world factors • Targeting real chips important • The field needs wild and crazy ideas – The vendors don’t have all the answers! • That requires custom CAD tools 2

The Challenge • Building custom physical CAD Tools for commercial FPGAs == difficult – Closed, proprietary device databases – Unsupported interfaces • Architectural nuances complicate things… 3

quality of result (QOR) Motivation #1: Rapid Prototyping seconds minutes hours tool runtime

quality of result (QOR) Motivation #1: Rapid Prototyping Commercial tools focus here… seconds minutes hours tool runtime

quality of result (QOR) Motivation #1: Rapid Prototyping For rapid prototyping and implementation we would like tools which focus here… Commercial tools focus here… seconds minutes hours tool runtime

Motivation #2: Reliability • SEU mitigation using TMR – Selective duplication tools – Single-bit TMR failures in routing • Half-latch detection – Weak keeper tie-offs susceptible to SEUs • Need a way to do post-PAR analysis • Need a way to do post-PAR modifications 7

XDL: A Physical Database for Xilinx • A textual design database representation – For Xilinx designs • Available for many years Custom CAD Tools 8

#1: XDL as a Design Representation • xdl –ncd 2 xdl design – Converts NCD to XDL • xdl –xdl 2 ncd design Custom CAD Tools – Converts XDL back to NCD • Can inject own CAD tools at any point in the flow or bypass it entirely • Must convert back to NCD for bitgen 9

#2: XDLRC as a Device Description • xdl -report -pips -all_conns part. Name – Dumps textual description of specific device as a. xdlrc file – Details everything you need to write placers and routers (except timing data) 10

Challenges of XDLRC Device Descriptions • They are massive! – Up to 73 GB of text for one device! – Difficult for tools to directly operate on XDLRC • They are missing some information – Primitive sites that support more than 1 type – Pin name mappings missing for some sites – Result: placement/routing inefficiencies occur • Rapid. Smith solves these problems 11

SOME TERMINOLOGY 12

A Familiar View of the Fabric… 13

A Familiar View of the Fabric… 14

A Familiar View of the Fabric… L_TERM INT_SO INT IOIS INT CLB INT INT CLB INT 15

XDLRC Abstraction – 2 D Tile Array 16

XDLRC Abstraction - Tiles HCLK_X 1 Y 39 INT_X 2 Y 37 CLB_X 2 Y 37 DSP_X 10 Y 32 BRAM_X 5 Y 32 17

XDLRC Abstraction – Primitive Sites INT_X 2 Y 37 Contains: TIEOFF_X 2 Y 37 CLB_X 2 Y 37 Contains: SLICE_X 3 Y 75 SLICE_X 3 Y 74 SLICE_X 2 Y 75 SLICE_X 2 Y 74 DSP_X 10 Y 32 Contains: DSP 48_X 0 Y 17 DSP 48_X 0 Y 16 BRAM_X 5 Y 32 Contains: RAMB 16_X 0 Y 8 FIFO 16_X 0 Y 8 18

XDL EXAMPLES 19

XDL Example inst "inst 23" "SLICEL", placed CLB_X 13 Y 45 SLICE_X 18 Y 91 cfg " BXINV: : BX BYINV: : #OFF. . . F: inst 23 lut 0: #LUT: D=((~A 1*A 3)+(A 1*A 2)) G: inst 23 lut 1: #LUT: D=((~A 1*A 3)+(A 1*A 4)). . . YUSED: : #OFF "; , . . . net "shift. Result 4" , cfg " ", inpin "inst 4" G 3 , outpin "inst 5" YQ , ; 20

XDL Example inst "inst 23" "SLICEL", placed CLB_X 13 Y 45 SLICE_X 18 Y 91 cfg " BXINV: : BX BYINV: : #OFF. . . F: inst 23 lut 0: #LUT: D=((~A 1*A 3)+(A 1*A 2)) G: inst 23 lut 1: #LUT: D=((~A 1*A 3)+(A 1*A 4)). . . YUSED: : #OFF "; , . . . net "shift. Result 4" , cfg " ", inpin "inst 4" G 3 , outpin "inst 5" YQ , pip CLB_X 31 Y 53 IMUX_B 18_INT -> G 3_PINWIRE 2 , pip CLB_X 31 Y 54 YQ_PINWIRE 2 -> SECONDARY_LOGIC_OUTS 6_INT , pip INT_X 31 Y 53 OMUX_S 3 -> IMUX_B 18 , pip INT_X 31 Y 54 SECONDARY_LOGIC_OUTS 6 -> OMUX 3 , ; 21

XDL Module Example module "mux" "inst 23" , cfg " _SYSTEM_MACRO: : FALSE "; port "mux 5 i_0_inport" "inst 31" "F 4"; port "mux 5 i_1_inport" "inst 33" "F 2"; . . . inst "inst 23" "SLICEL", placed CLB_X 13 Y 45 SLICE_X 18 Y 91 , cfg " BXINV: : BX BYINV: : #OFF. . . YUSED: : #OFF "; . . . net "shift. Result 4" , cfg " ", inpin "inst 4" G 3 , outpin "inst 5" YQ , pip CLB_X 31 Y 53 IMUX_B 18_INT -> G 3_PINWIRE 2 , pip CLB_X 31 Y 54 YQ_PINWIRE 2 -> SECONDARY_LOGIC_OUTS 6_INT , pip INT_X 31 Y 53 OMUX_S 3 -> IMUX_B 18 , pip INT_X 31 Y 54 SECONDARY_LOGIC_OUTS 6 -> OMUX 3 , ; endmodule "mux"; 22

THE RAPIDSMITH TOOL SUITE 23

Rapid. Smith XDL File 24

Rapid. Smith XDL File Internal Graph Represenation Java API Rapid. Smith XDL File 25

Rapid. Smith XDL File Custom Cad Tools Internal Graph Represenation XDL File Java API Rapid. Smith ( create, place, route, modify circuits ) 26

Rapid. Smith Abstractions Design Device Instance Net Module Primitive. Type Net. Type Port (List) Instance (List) Attribute (List) Pin (List) Instance (List) Net (List Primitive. Site PIP (List) Net (List) XDL Tile (2 D Array) Module. Instance Tile. Type Primitive. Site (Array) Wire Primitive. Type Tile XDLRC 28

XDLRC Device File Creation • Three major strategies to reduce XDLRC information size: – Aggressive wire and object reuse – Careful pruning of unnecessary wires – Customized serialization and compression • XDLRC size compression of >10, 000 X • Device files load in just a few seconds or less 29

Rapid. Smith Device Files Performance Xilinx Part Name Virtex 4 LX 200 XDLRC Rapid. Smith Memory Report Size File Size Footprint 10. 0 GB 1. 01 MB 61 MB Load Time From Disk 602 ms Virtex 5 LX 330 12. 5 GB 1. 07 MB 69 MB 622 ms Virtex 6 CX 240 T 8. 5 GB 0. 94 MB 35 MB 460 ms Virtex 6 LX 760 22. 8 GB 1. 76 MB 77 MB 1. 07 s Virtex 7 855 T 32. 0 GB 2. 63 MB 115 MB 1. 41 s Virtex 7 2000 T 73. 6 GB 5. 96 MB 301 MB 3. 34 s 30

7 EXAMPLES OF RAPIDSMITH USE AND CAPABILITIES 31

Rapid. Smith Example #1: Random Placer public class Random. Placer{ public static void main(String[] args){ // Create and load a design Design design = new Design(args[0]); Random rng = new Random(0); // Create random number generator // Place all unplaced instances for(Instance i : design. get. Instances()){ if(i. is. Placed()) continue; Primitive. Site[] sites = design. get. Device(). get. All. Compatible. Sites(i. get. Type()); int idx = rng. next. Int(sites. length); int watch. Dog = 0; // Find a free primitive site while(design. is. Primitive. Site. Used(sites[idx])){ if(++idx > sites. length) idx = 0; if(++watch. Dog > sites. length) System. out. println("Placement failed. "); } i. place(sites[idx]); } // Save the placed design. save. XDLFile(args[1]); } 32 }

Rapid. Smith Example #2: Placing a Module // Load XDL file (parses XDL, populated design object) Design design = new Design("module. Containing. Design. xdl"); // Get the 1024 -FFT module definition by name Module fft = design. get. Module("fft 1024"); // Create an instance of the FFT module called "f 0" Module. Instance mi = design. create. Module. Instance("f 0", fft); //Find all compatible sites with the anchor Primitive. Type type = mi. get. Anchor(). get. Type(); Primitive. Site[] sites = design. get. Device(). get. All. Compatible. Sites(type); int i = 0; while(!mi. place(sites[i++], design. get. Device())){ if(i >= sites. length) error(mi. get. Name()+ " has no valid placement!"); } 33

Rapid. Smith Example #3: VCC/GND Handling • GND/VCC supplied in two ways: – LUTs configured to drive ‘ 1’ or ‘ 0’ – TIEOFF primitives in every switch box • Supplied GND / VCC posts • Router must partition nets into neighborhoods to use local static sources – Rapid. Smith includes a Static. Source. Handler class with a variety of methods to provide this functionality 34

Rapid. Smith Example #4: HMFlow • Rapid compilation approach using hard macros • Built on top of Rapid. Smith Design Parser & Mapper . mdl Design Stitcher XDL Hard Macro Placer XDL Router NPUT DESIGNS Generic HMG . xdl PLACED & ROUTED XDL Part of CHREC research project HM Cache HARD MACRO SOURCES Demonstrated > 50 X reduction in tool flow time 35

Rapid. Smith Example #5: Device Browser 36

Rapid. Smith Example #6: Design Explorer 37

Rapid. Smith Example #7: Custom Hard Macro Placer 38

Rapid. Smith Example #7: Timing Visualizer

Conclusion • Rapid. Smith – Provides XDL-based infrastructure – Designed to aid in the construction of custom CAD tools • Flexible – Custom CAD flow • HMFlow for Hard Macro-Based Design – Custom individual steps in the flow • Placer or router – Post Xilinx flow circuit modifications • Reliability modifications – Post Xilinx flow circuit analysis • Timing visualization • Available open source: – http: //rapidsmith. sourceforge. net 40