Rapid Prototyping Design Process Module Goals

Rapid Prototyping Design Process

Module Goals

Module Outline

Module Outline

Module Outline

Hardware Synthesis

Definitions

Definitions (Cont. )

Definitions (Cont. )

Synthesis Goals

Synthesis Constraints

Synthesis Processes

Synthesis Categories

Behavioral Synthesis * *

Behavioral Synthesis (cont. ) * * *

RTL Level Synthesis *

Logic Synthesis

Module Outline

Module Outline

Types

Types (cont. )

Attributes

Concurrent Signal Assignment Statements

Conditional Signal Assignment Statements

Selected Signal Assignment Statements

Operators

Operators (cont. )

Operators (cont. )

Process Statements

Sequential Signal Assignment Statements

Sequential IF Statements

Sequential Case Statements

Sequential Loop Statements

Procedures and Functions

Procedures and Functions (cont. )

Procedures and Functions (cont. )

Using Procedures and Functions

Using Procedures and Functions (cont. )

Tri-State Logic

Use of Don’t Cares (‘X’s)

After Clauses

Inferring Latches

Avioding Latches

Module Outline

Level Sensitive D Latch

Edge Sensitive D Flip-Flop

Edge Sensitive D Flip-Flop (cont. )

Edge Sensitive Flip-Flops

Edge Sensitive Flip-Flops

Finite State Machine Synthesis

Mealy and Moore State Machine Models

State Machine Simple Example State Diagram

Sequential Datapaths

Flow Chart for Unsigned 8 Bit Multiplier Controller

State Diagram for Unsigned 8 Bit Multiplier Controller

Module Outline

RTL Level Synthesis

Floating Point Multiplier Code

Floating Point Multiplier Code

Floating Point Multiplier Code

Floating Point Multiplier Code

Floating Point Multiplier Code

Module Outline

Structural VHDL

Module Outline

Implementation Technology Considerations

Module Outline

Summary

Summary (cont. )

References