PSP Family of Compact Models Overview and Recent

PSP Family of Compact Models Overview and Recent Developments MOS-AK December 13 th, 2008 G. Gildenblat, W. Wu, X. Li, Z. Zhu, W. Yao, Q. Zhou, G. Dessai, and A. Dey G. D. J. Smit, A. J. Scholten, and D. B. M. Klaassen 1

Outline § PSP project overview § Introduction to bulk PSP § Recent developments in bulk PSP § PSP-SOI § PSP-MGFET § Conclusions MOSFET characteristics shown in this presentation are from Philips/NXP, Freescale and IBM (presented with permission) Further information about PSP can be found on PSP website: http: //pspmodel. asu. edu 2

PSP Family of Models § PSP: industry (CMC) standard for bulk MOSFETs § PSP-based varactor model: industry (CMC) standard § PSP-SOI-PD: submitted to CMC for evaluation (sponsored by IBM) § PSP-SOI-DD: submitted to CMC for evaluation (sponsored by Freescale) § PSP-MGFET § PSP-LT: PSP model for the extended temperature range for space applications (NASA/JPL) § PSP-R 2 H: PSP-based model for the physics-based real-time evaluation of radiation, EMP and reliability effects at the circuit level 3

Outline § PSP project overview ► Introduction to bulk PSP § Recent developments in bulk PSP § PSP-SOI § PSP-MGFET § Conclusions 4

s-Based vs. Vth-Based Models PSP Vth-based VSB = 0 V; VDS = 1 V 5

Advanced Features of PSP § Non-iterative formulation § Completely surface-potential-based including the S/D overlap regions § Complete symmetry of device characteristics including all higherorder effects § Advanced mobility model including Coulomb scattering § Perfect reproduction of gm/Id ratio § Capability to model harmonic distortion including intermodulation effects § Physical gate current model including accurate bias-dependent partitioning scheme implemented via symmetric linearization method 6

Advanced Features (cont’d) § The most complete ever noise model correctly including velocity saturation effects and all noise sources § Extensively verified unified large-signal/small signal NQS Model § Most complete and physical junction diode model (JUNCAP 2) § Inclusion of non-uniform doping § Accurate CLM modeling in halo-doped devices § New mathematical structure of the model based on solution of several long-standing problems of compact modeling (e. g. symmetric linearization, spline-collocation NQS model, etc. ) 7

Normalized Mobility Non-Universality of the Effective Mobility Produced by the Coulomb Scattering Produced by Coulomb Scattering Term Effective Field (MV/cm) 8

Drift Velocity § PSP uses drift velocity model that is conducive to the highly accurate description of saturation region including high order drain conductances Electrons: Holes: § This form also assures compliance with Gummel symmetry test and non-singular model behavior at Vds= 0. 9

Gm / ID (1/V) Gm/ID Plots for Two Corners of the 90 nm Process 10µm/1µm ID (A) 10µm/0. 04µm ID (A) VDS = 0. 025 V, VBS = 0 to -1. 2 V, and VGS = 0 to 1. 2 V 10

Output Conductances W/L=10/0. 04µm g. DS (A/V) W/L=10/1µm VDS (V) VGS = 0 V to 1 V in steps of 0. 2 V, VSB = 0 V T = 250 C 11

gmi (A/V) g. DSi (A/V) Higher Order Transconductances and Conductances VDS = 0. 025 V VGS (V) VSB=0 V, T=250 C, W/L=10/0. 04µm (nmos), i=1(lower curve), 2(middle curve), 3(upper curve) VGS = 1 V VDS (V) VSB=0 V, T=250 C, W/L=10/0. 04µm (nmos), i=1(lower curve), 2(middle curve), 3(upper curve) 12

Traditional Asymmetric Linearization § Theoretical foundation of PSP is symmetric linearization method: it is used to simplify surface-potential-based approach and to make it practical. § To simplify formulation compact MOSFET models almost always use bulk and inversion charge linearization. The traditional form is § In Vth-based models: § Disadvantage: symmetry between source and drain is lost, accuracy is poor 13

Symmetric Linearization § Define surface potential midpoint (subscript “m”) § For VDS > 0, this is not a geometric midpoint: § Set inversion charge (per unit channel area) 14

Example of What Symmetric Linearization can Accomplish § Original CSM (C. Mc. Andrew and J. Victory, 2003) § PSP 15

Verification of Symmetric Linearization Vds = 2 V, Vbs= 0 V, Vfb=1 V 16

CV Characteristics Vds (V) W/L=10/0. 08µm, Vbs=-0. 1 V, Vgs=1. 2 V W/L = 800µm/90 nm, Vds=0, Vsb=0 17

Gate Tunneling Current Components § The same form of model and identical parameters are used in Igc, Igsov and Igdov § No scaling parameters are required to fit the data VDS=0 V to 1 V in steps of 0. 5 V VSB=0 V, W/L=10µm/1µm (nmos) T=250 C 18

PSP Noise Model § Includes thermal channel noise, 1/f noise, channel-induced gate noise and shot-noise in the gate-current § Example § Thermal channel noise automatically becomes shot noise below threshold, so it is not necessary to model this phenomena separately § Rigorously includes fluctuations in the velocity saturation term. § Takes advantage of symmetric linearization to simplify expressions for the spectral densities § Experimentally verified Drain (Sid) and gate (Sig) current noise spectral densities 19

NQS Model Verification: Re[Y 11] PSP, SWNQS=5 PSP, SWNQS=9 MM 11, 5 segments VDS=1. 5 V, VGS= 0. 5 to 1. 5 in 0. 5 V steps 20

Outline § PSP project overview § Introduction to bulk PSP ► Recent developments in bulk PSP § PSP-SOI § PSP-MGFET § Conclusions 21

Recent Developments in PSP § Optional asymmetric junctions § Optional separate doping profiles for I(V) and C(V) characteristics § Optional suppression of back-bias effect for high back biases § GA-based automatic procedure for parameter extraction (local and global) § PSP-LT: PSP model for the extended temperature range 22

Automatic GA LM Parameter Extraction § GA - Genetic Algorithm, LM - Levenberg Marquardt Algorithm § Objectives • Unbiased evaluation of new parameters (are they really needed) • Ease of parameter extraction § Example : Table I. Relative RMS error (%) on Id (Vd) with ALP 2 on and off. Setting Fit with ALP 2=0 Fit with ALP 2 0 W=L=10 m W/L=10/0. 24 m W/L=10/0. 06 m 1. 6 0. 63 2. 9 1. 7 2. 5 1. 8 23

Automatic Parameter Extraction Results for PSP 102. 1 W=L=10 m W/L=120/65 nm W=L=10 m W/ L=120/65 nm 24

L = 45 nm VDS = 50 m. V VSB = 0 … 1. 3 V Ids (arb. units) Non-uniform Doping PSP 102 PSP 103 with NUD measured PSP 0. 0 0. 5 VGS (V) 1. 0 25

Non-uniform Doping Effective body factor Threshold voltage 26

Decouple C-V and I-V Using a Separate NSUB for both I-V and C-V single effective N I-V and C-V Shift of Vth due to lateral halo doping New C-V fit does not affect I-V Achieve better fit using alternative NSUB for C-V only An IBM process using halo doping (from J. Watts) 27

Parameter Extraction Flowchart For PSP 103 28

Outline § PSP project overview § Introduction to bulk PSP § Recent development in bulk PSP ► PSP-SOI § PSP-MGFET § Conclusions 29

Impact of EVB on DC-IV § EVB affects IDS linearity at high VGS § Model can faithfully reproduce the “humps” in gm characteristics W/L = 3 m/0. 13 m 30

Parasitic BJT § q. B incorporates the Early effect and high level injection § Recombination current in neutral body region § Junction diffusion capacitance G S D body BOX VE=VS=0 V VG= -0. 3 V VD=VB Substrate W/L = 3 m/0. 055 m 31

Bias-Dependent Body Resistance Model § Bias independent Q Bf S § Bias dependent tox G Qjs Qnbr D Qjd L tsi tbox Substrate Based on Freescale in-house Rbody model (G. Workman et al. ) § Mobile charges in neutral body region § Total bulk charge § B: mobility of majority carriers in the body § Qnbr: total mobile majority charge in the neutral body region 32

Example: 65 nm PD/SOI H-gate IS Bs S G D Junction leakage + - Bf If VBS W/L = 3 m / 65 nm VGS = -0. 3 V; VDS = 0 V 33

Excess Low Frequency Noise Modeled Automatically § Excess LF noise is caused by floating body effect W. Jin et al T-ED 1999 Excess noise VDS=0. 6, 0. 7, 0. 8, 0. 9 V G S CGB CSB D CDB req PD/SOI floating body W/L = 3 m/0. 055 m CEB E 34

Body-Contacted PD/SOI VGS= 0. 2, 0. 4, 0. 6, 0. 8, 1. 0, 1. 3 V VBS = 0. 0 V L=150 nm W=3 m, L=55 nm-150 nm 75 nm 65 nm 55 nm 35

BC PD/SOI Cont’d VBS= -0. 2, 0, 0. 2, 0. 4, 0. 6 V VDS= 0. 05 V L=150 nm 75 nm 65 nm 55 nm 36

PSP-SOI-PD Harmonic Balance Simulation PD/SOI floating body; W/L = 3 m/0. 055 m 37

Outline § PSP project overview § Introduction to bulk PSP § Recent development in bulk PSP § PSP-SOI ► PSP-MGFET § Conclusions 38

DGFET and SGFET Structures Double Gate Surrounding Gate 39

Symmetric Linearization for DGFET SL formulation: 40

Symmetric Linearization for SGFET 41

Conclusions § Surface-potential-based approach to MOSFETs of all kinds is an undisputed industry standard § PSP model includes all relevant device physics and its accuracy is verified down to 32 nm technology node § PSP model structure is flexible and is easily extendable to enable the model to serve as gateway for advanced CMOS design in the coming years § Work is in progress to add the latest developments and to maintain and upgrade the model code § PSP family includes bulk, varactor, SOI and Fin. FET models 42

Acknowledgements § PSP developers are grateful to C. Mc. Andrew, P. Bendix, J. Watson, and G. Workman for numerous stimulating discussion of the subject of compact modeling § The development of PSP is continuously funded in part by SRC since 1998 § Testing and implementation of PSP is funded in part by CMC § Past funding from LSI Logic, Mentor Graphics, Freescale, IBM and TI is gratefully acknowledged 43