PSo. C 3 / PSo. C 5 101: Architecture Overview Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 1
Section Objectives, you will: • Understand the high-level architecture of PSo. C 3 / PSo. C 5 • Understand the CPU, Digital, Analog & Programmable Routing / Interconnect Subsystems Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 2
PSo. C 3 / PSo. C 5 Platform Architecture Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 3
CPU Subsystem ARM Cortex-M 3 • Industry’s leading embedded CPU company • Broad support for middleware and applications • Up to 80 MHz; 100 DMIPS • Enhanced v 7 ARM architecture: • Thumb 2 Instruction Set • 16 - and 32 -bit Instructions (no mode switching) • 32 -bit ALU; Hardware multiply and divide • Single cycle 3 -stage pipeline; Harvard architecture 8051 • Broad base of existing code and support • Up to 67 MHz; 33 MIPS • Single cycle instruction execution Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 4
CPU Subsystem High Performance Memory • Flash memory with ECC • High ratio of SRAM to flash • EEPROM Powerful DMA Engine • 24 -Channel Direct Memory Access • Access to all Digital and Analog Peripherals • CPU and DMA simultaneous access to independent SRAM blocks On-Chip Debug and Trace • Industry standard JTAG/SWD (Serial Wire Debug) • On chip trace • NO MORE ICE Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 5
CPU Subsystem Clocking System • Many Clock Sources • Internal Main Oscillator • External clock crystal input • External clock oscillator inputs • Clock doubler output • Internal low speed oscillator • External 32 k. HZ crystal input • Dedicated 48 MHz USB clock • PLL output • 16 -bit Clock Dividers • 8 Digital • 4 Analog • PSo. C Creator Configuration Wizard • PSo. C Creator auto-derive clocking source/dividers Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 6
CPU Subsystem Dedicated Communication Peripherals • Full Speed USB device • 8 bidirectional data end points + 1 control end point • No external crystal required • Drivers in PSo. C Creator for HID class devices • Full CAN 2. 0 b • 16 RX buffers and 8 TX buffers • I 2 C master or slave • Data rate up to 400 kbps • Additional I 2 C slaves may be implemented in UDB array • New peripherals will be added as family members are added to the platform: Ethernet, HS USB, USB Host… Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 7
CPU Subsystem Power Management • Industry’s Widest Operating Voltage • 0. 5 V to 5. 5 V with full analog/digital capability • High Performance at 0. 5 V • PSo. C 3 @ 67 MHz; PSo. C 5 @ 72 MHz • 3 Power Modes (Active, Sleep and Hibernate) Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 8
Designed for Low Power/Low Voltage On-board DMA Controller Highly configurable clock tree Direct memory transfer between peripherals offloads CPU operation, lowering power consumption Flexible, automated clock gating. Universal Digital Blocks Implement features in hardware that reduce CPU processing requirements, lowering power consumption Cached Operations Execution from flash memory is improved by caching instructions (PSo. C 5 only) Precise CPU frequencies PLL allows 4, 032 different frequencies; tunable power consumption Integrated Analog, Digital and Communication Peripherals Reduce external component counts and lower overall system power consumption Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 9
Low Power Modes Power mode Current (PSo. C 3) Current (PSo. C 5) Active 1. 2 m. A @ 6 MHz Digital Code resources execution available Yes All Sleep 1 u. A 2 u. A No I 2 C Hibernate 200 n. A 300 n. A No None Analog resources available Clock sources available Wakeup sources Reset sources All N/A All IO, I 2 C, RTC, XRES, LVD, Low Speed and WDR Comparator sleep timer, 32 k. Hz Osc comparator None IO XRES, LVD Power Management Enabled in PSo. C Creator • Provides easy to use control APIs for quick power management • Allows code and register manipulation for in-depth control Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 10
Digital Subsystem Universal Digital Block Array (UDBs) • Flexibility of a PLD integrated with a CPU • Provides hardware capability to implement components from a rich library of pre-built, documented, and characterized components in PSo. C Creator • • • PSo. C Creator will synthesize, place, and route components automatically. 32 -bit PWM GP Logic 16 -bit PWM GP Logic UART #3 GP Logic Fine configuration granularity enables high silicon utilization DSI routing mesh allows any function in the UDBs to communicate with any other on-chip function/GPIO pin with 8 - to 32 -bit data buses UART #1 GP Logic UART #2 LCD Segment Drive GP Logic I 2 C Slave 16 -bit Shift Reg. GP Logic Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H SPI Master 11
Digital Subsystem Optimized 16 -bit Timer/Counter/PWM Blocks • • Provides nearly all of the features of a UDB based timer, counter, or PWM PSo. C Creator provides easy access to these flexible blocks Each block may be configured as either a full featured 16 -bit Timer, Counter, or PWM Programmable options • • • Clock, enable, reset, capture, kill from any pin or digital signal on chip Independent control of terminal count, interrupt, compare, reset, enable, capture, and kill synchronization Plus • • Configurable to measure pulse widths or periods Buffered PWM with dead band kill Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 12
Analog Subsystem Configurable Analog System • • • Flexible Routing: All GPIO are Analog Input/Output +/- 0. 1% Internal Reference Voltage Delta-Sigma ADC: Up to 20 -bit resolution • 16 -bit at 48 ksps or 12 -bit at 192 ksps SAR ADC: 12 -bit at 1 Msps DACs: 8 – 10 -bit resolution, current and voltage mode Low Power Comparators Opamps (25 m. A output buffers) Programmable Analog Blocks • Configurable PGA (up to x 50), Mixer, Trans-Impedance Amplifier, Sample and Hold Digital Filter Block: Implement HW IIR and FIR filters Cap. Sense Touch Sensing enabled Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 13
Programmable Routing/Interconnect Input / Output System • Three types of I/O • GPIO, SIO, USBIO • Any GPIO to any peripheral routing • Wakeup on analog, digital or I 2 C match • Programmable slew rate reduces power and noise • 8 different configurable drive modes • Programmable input threshold capability for SIO • Auto and custom/lock-able routing in PSo. C Creator Up to 4 separate I/O voltage domains • Interface with multiple devices using one PSo. C 3 / PSo. C 5 device Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 14
PSo. C 3 / PSo. C 5 Platform Architecture Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 15
Review You should now: • Understand the high-level architecture of PSo. C 3 / PSo. C 5 • Understand the CPU, Digital, Analog & Programmable Routing / Interconnect Subsystems Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 16
Lab 101: My First PSo. C 3 Digital Design Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 17
Lab Objectives: • Blink an LED on the PSo. C First Touch Kit • Experience the PSo. C Creator Design Flow Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 18
Step 1: Start PSo. C Creator Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 19
Step 2: Create a New Project Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 20
Step 3: Place/Configure Digital Pin Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 21
Step 3: Place/Configure Digital Pin Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 22
Step 4: Configure PSo. C I/O Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 23
Step 5: Add main. c Code Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 24
Step 5: Add main. c Code Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 25
Step 6: Build Project Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 26
Step 7: Program/Debug Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 27
Step 8: Debug Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 28
PSo. C 3 / PSo. C 5 101: PSo. C Creator Design Flow Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 29
Section Objectives, you will be able to: • Follow the PSo. C Creator Design Flow and develop projects • Find and use the tools available within the software IDE • Compile, build and program PSo. C 3 / PSo. C 5 applications • Debug PSo. C 3 / PSo. C 5 applications Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 30
PSo. C Creator Design Flow Configure • • Start a new project Place components Configure components Connect components Develop • Build hardware design and generate component APIs • Write application code utilizing component APIs • Compile, build and program Debug • Perform in-circuit debug using PSo. C Creator Reuse • Capture working hardware/software designs as your own components for future use Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 31
Open PSo. C Creator Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 32
PSo. C Creator Software Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 33
Create a new project Select the platform Name the design Select the device* Select the sheet template* * Optional steps Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 34
PSo. C Creator Design Canvas Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 35
Component Catalog Folders Analog ADC Amplifier DAC Digital Registers Functions Logic Communication Display System Catalog Preview Datasheet access Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 36
Adding Components to a Design Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 37
Pins, Logic and Clock Components Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 38
Component Configuration Double-click to open component configuration dialogs Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 39
Component Data Sheets Contents: • • • Features General description of component When to use component Input/Output connections Parameters and setup Application Programming Interface Sample firmware source code Functional description DC and AC electrical characteristics Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 40
Design-Wide Resource Manager (. cydwr) Clocks Interrupts • Set priority and vector DMA • Manage DMA channels System • Debug, boot parameters, sleep mode API generation, etc. Directives • Over-ride placement defaults Pins • Map I/O to physical pins and ports • Over-ride default selections Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 41
Interrupts Priority may be changed Defaults to 7 (lowest priority) Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 42
DMA Priority may be changed Defaults to 2 (0 & 1 can consume 100% of bandwidth) Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 43
System settings Debug settings Voltage Configuration Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 44
System Clocking Tree Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 45
Clock Configurations Clocks are allocated to slots in the clock tree • 8 digital, 4 analog Clocks have software APIs Reuse existing clocks to preserve resources Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 46
Pin Editor Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 47
Connecting Components Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 48
Build Hardware Design Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 49
Build Process Generate a Configuration • • • Design Elaboration Netlisting Verilog Logic Synthesis Technology Mapping Analog Place and Route Digital Packing Digital Placement Digital Routing <…there’s more…> Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 50
Build Process API Generation Compilation Configuration Generation Configuration Verification Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 51
Development Files Core Cypress Libraries (Cy. Lib) Registers, macros, types (cytypes) Component addressing (cyfitter) Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 52
Supported Compilers Free Bundled compiler options PSo. C 3: Cypress-Edition Keil™ CA 51 Compiler Kit PSo. C 5: GNU/Code. Sourcery G++™ Lite No code size restrictions, not board-locked, no time limit Fully integrated including full debugging support GNU Upgrade, more optimization/compiler-support options PSo. C 3: Keil CA 51™ Compiler Kit PSo. C 5: Keil Real. View® Microcontroller Development Kit Higher levels of optimization Direct support from the compiler vendor Upgrade Compiler Pricing Set and managed by our 3 rd party partner, Keil Already own these compilers? No need to buy another license! Keil CA 51 Compiler Kit ~$2, 000 Keil Real. View MDK ~$3, 000 -5, 000 Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 53
Integrated Debugger JTAG and SWD connection • All devices support debug • Mini. Prog 3 programmer / debugger Control execution with menus, buttons and keys Full set of debug windows • Locals, register, call stack, watch (4), memory (4) • C source and assembler • Components Set breakpoints in Source Editor Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 54
Debugger Windows Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 55
Mini. Prog 3 • • Program PSo. C 1 devices Program/Debug PSo. C 3 / PSo. C 5 devices Standard 50 mil connector n. TRST/XRES pin is used as the device reset (XRES) by default • n. TRST is JTAG specific and rarely used 2 x 5 50 mil ISSP/JTAG/SWD/ SWV/Trace. Port ribbon cable and connector ISSP connector Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 56
PSo. C Development Kit (CY 8 CKIT-001) • Supports all PSo. C architectures via processor modules • Integrated support of all required and optional chip connections • Mini. Prog 3 should not supply power to PSo. C Development Kit Independent digital, analog and IO supply rails (current measurement 3. 3 V, 5. 0 V and adjustable 1. 8 V– 5. 0 V regulators supported) RS-232 Three expansion ports support 28 IO each + 45 IO USB for target PSo. C Processor Modules RF Module Radio header 1 Pot, 2 buttons, 4 LEDs, 2 x 16 LCD Cap. Sense Slider & Buttons Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 57
Review You should now be able to: • Follow the PSo. C Creator Design Flow and develop projects • Find and use the tools available within the software IDE • Compile, build and program PSo. C 3 / PSo. C 5 applications • Debug PSo. C 3 / PSo. C 5 applications Introduction to PSo. C 3 / PSo. C 5 Workshop – Rev *H 58