Progress in the North American Solid State Tracking

Progress in the North American Solid State Tracking R&D program Rene Bellwied (Wayne State University) for the North American Solid State groups International Linear Collider Tracking Review Amsterdam, March 31 st, 2003 Proposed layout for LC tracker Silicon Drift technology hardware progress & plans Silicon Strip technology hardware progress & plans Simulation update Alignment monitoring project Summary and Outlook

Silicon detector option for LCD (small detector, high field B=5 T) Central tracker: Five Layer Device based on Silicon Drift or Silicon Strip Wafers Radiation length / layer = 0. 5 %, sigma_rphi = 7 mm, sigma_rz = 10 mm Layer Radii Half-lengths ------------ 20. 00 cm 26. 67 cm 46. 25 cm 61. 67 cm 72. 50 cm 96. 67 cm 98. 75 cm 131. 67 cm 125. 00 cm 166. 67 cm 56 m 2 Silicon, Wafer size: 10 by 10 cm, # of Wafers: 6000 (incl. spares) # of Channels: 4, 404, 480 channels

Project I: Silicon Drift Tracker (SDT) l Participants: Wayne State University (WSU) & Brookhaven National Laboratory (BNL) l l l BNL Physics: V. Jain, F. Lanni, D. Lissauer BNL Instrumentation: W. Chen, Z. Li, V. Radeka WSU: R. Bellwied, D. Cinabro, M. Coscione, V. Rykov (KEK) + new postdoc Funding: 3 -year NSF proposal (pending, positive review): 2003 -2005 for a total of $450 K ($ 80, 170, 200 K). Previously we had limited NSF funding for two years. Hardware contribution per year (for BNL): $ 25, 50, 90 K Check out the web at: http: //rhic 15. physics. wayne. edu/~bellwied/nlc

SDD’s: 3 -d measuring devices Features: Low anode capacitance = low noise 3 d information with 1 d readout Pixel-like by storing 2 nd dimension in SCA Low number of RDO channels based on charge sharing in use in STAR (RHIC), in construction for ALICE (LHC)

SVT in STAR l l l 216 wafers (bi-directional drift) 3 barrels, r = 5, 10, 15 cm, 103, 680 channels, 13, 271, 040 pixels Resolution: 8 micron and 17 micron respectively, two-track: 150 micron Radiation length: 1. 4% per layer l 0. 3% silicon, 0. 5% FEE (Front End Electronics), l 0. 6% cooling and support. Beryllium support structure. l FEE placed adjacent to wafers. No driving capability in very high resistivity n-type NTD Silicon. Water cooling.

Typical SDD Resolution n n Bench measurements now confirmed by STAR beam time results ! (Feb. 03) Can be improved through: n n faster drift, stiffer resistor chain for voltage gradient, different anode pitch, and better starting material achieved with one-dimensional readout with 250 mm pitch

Proposed wafer R&D n l l Present: 6 by 6 cm active area = max. 3 cm drift, 3 mm (inactive) guard area Max. HV=1500 V, max. drift time=5 ms anode pitch = 250 mm, cathode pitch = 150 mm n n n Future: 10 by 10 cm active area (or more ? ) Max. HV=2000 V Anode pitch, cathode pitch have to be optimized to give better position resolution (more channels = more money) Stiffer resistor chain dissipates slightly more heat on detector, but requires no off detector HV support and allows a more linear drift in drift direction (better position resolution) Reduce wafer thickness from 280 micron to 150 micron.

Details of mask design Future: stiffer implanted resistors, no outside power supplies R. Bellwied, June 30, 2002

Proposed Frontend (FEE) R&D n n n Present: bipolar PASA & CMOS-SCA ( 16 channel per die, 15 die for 240 channels on beryllia substrate ) Multiplexing on detector, 8 bit ADC off detector (3 m) Future: 0. 25 micron (DSM) radiation hard CMOS technology for all three stages in one single chip (PASA, SCA, 10 -bit ADC) Example: ALICE-PASCAL Less power consumption and power cycling allows us to switch from liquid cooling to air cooling !

Proposed mechanical R&D n n Present: Be angled brackets with Beryllia hybrids mounted Future: carbon fiber staves with TAB electronics wraparounds

Capabilities & Industry contacts l In house capabilities l l l Industry contacts l l High quality clean room facilities for design and prototyping of wafers and electronics at BNL Instrumentation division High level CMOS engineering capabilities at BNL Instrumentation Sensor testing facilities at WSU, Ohio State, and UT Austin Dedicated electronics testing facilities at BNL Physics Dedicated mechanical assembly facilities (CMM & CNC devices) at BNL Physics plus expert machine shop at BNL Past production contracts with commercial drift detector vendors: SINTEF, CSEM, EUROSYS, CANBERRA Potential interests: MICRON, HAMAMATSU Carbon fiber machining capabilities in house and in US, France & Russia Potential interest in scientific collaboration in France and Italy (LHCALICE groups)

Hardware deliverables in present 3 year proposal 2003 hardware deliverables: new drift detector wafer layout according to R&D goals. Feasibility study of BNL stripixel technology vs. drift detectors. long ladder prototype with old drift wafers (mechanical feasibility) l 2004 hardware deliverables: large batch of prototype detectors, test radiation damage in test beam and with sources. Beginning design of new frontend electronics l 2005 hardware deliverables: complete design for CMOS DSM type frontend with reduced power consumption and potentially integrated ADC, test TAB bonding of frontend to detector prototype, produce large frontend prototype batch. Extensive test beam requirements for completed detector/FEE combination by end of 2005. l

Stripixels: alternative from BNL ? Alternating Stripixel Detector (ASD) Interleaved Stripixel Detector (ISD) Pseudo-3 d readout with speed and resolution comparable to double-side strip detector on single-sided technology (Zheng Li, BNL report, Nov. 2000). Attractive for faster speed and easier to manufacture than double-sided strip

Project II: Long Shaping Time Si-strip Readout Participants: Dave Dorfan, Christian Flacco, Alex Grillo, Hartmut Sadrozinski, Bruce Schumm, Abe Seiden, Ned Spencer, Lan Zhang (UC Santa Cruz) Also, a new post-doc (Gavin Nesom) will join the effort in April Potential external associates: SLAC, LPNHE Paris, CERN RD 50 Funding: 2 -year, $90, 000 grant from the DOE Advanced Detector R&D Program (funded through 2003, will need to enter regular LC funding game afterwards)

Present scope of project Broad scope: • 9 months graduate student support • Chip fabrication • Long-ladder development (existing sensors) • Electronics servicing to ladder Detailed ‘deliverables’: - Characterization of analog characteristics of 0. 25 micron structures - Development of pulse development and electronic simulation for shaping-time and readout-scheme optimization - Demonstration of noise level commensurate with readout of 1 -2 m ladder - Demonstration of x 100 suppression of IR heating loss - Min-i readout of long ladder

Motivation Use of long shaping-time read-out (low noise) plus exploitation of duty cycle permits development of very long, thin ladders with small power consumption. Additionally, limited readout and servicing may lead to very limited material budget in forward region (down to 100 mrad) The limit of the maximum shaping time is given by consideration of: - dynamic range in terms of time over threshold (TOT) - sufficient power cycling time - shot noise Present goal: shaping times of 2 -5 ms

Anticipated noise levels Agilent 0. 5 mm CMOS process (qualified by GLAST) Min-i for 300 mm Si is about 24, 000 electrons Shaping (ms) 1 1 3 3 10 10 Length (cm) 100 200 Noise (e-) 2200 3950 1250 2200 1000 1850

Pulse Development Simulation Effects incorporated: • Landau fluctuations (SS_Sim. SId. E, Jerry Lynch, LBNL) • Carrier (hole) diffusion / space-charge repulsion • Lorentz angle, Electronic noise, Pulse digitization / reconstruction Questions to be answered: • Signal-to-noise for long ladders, optimal sensor geometry & detector bias • Evaluation of analog readout scheme (TOT, direct analog, least-bit, etc. ; <7 mm resolution) • Effect of large magnetic fields, effects of oblique angles of incidence

TOT given by difference between two solutions to TOT/t Example: Time-Over-Threshold (TOT) (RC-CR shaper) Digitize with granularity t/ndig q/r

Result: S/N for 167 cm Ladder Ep = 1 -1. 5 Ge. V At threshold of 0. 3*min-I: Eff. : 99. 9%, noise occupancy: 0. 1% (at shaping time of 3 ms; 0. 5 mm process qualified by GLAST)

Short term / long term plans Immediately: - begin SPICE-level optimization of shaping time (assuming 1 -2 meter ladder) - have already begun qualifying GLAST 8 -channel `cutoff’ structures for use in 2 m ladder April: begin mechanical design and construction of 2 m ladder June-July: submission of prototype ASIC Fall 2003: measure noise and power consumption characteristics Winter 2003 (likely): begin design of 2 nd prototype chip based on accumulated experience Winter 2004: begin development of realistic prototype ladder, prepare for testbeam run Summer 2004: testbeam studies; begin to develop scheme for back-end architecture

Simulation update: L vs. SD

Simulation update: hit occupancy on single wafer Using STAR detector layout and LC simulations (t -tbar to 6 jet events at root-s = 500 Ge. V incl. g background according to T. Maruyama): n n n Around 2000 g/event leave hit in Silicon, corresponding to an occupancy of 13 hits/hybrid (0. 5% occupancy) 51, 200 pixels per hybrid, 20 pixels/hit Occupancy could be further reduced by factor 2 by using different SCA

Occupancies and tracking efficiencies with background For 100% hit efficiency: (97. 3± 0. 10)% Almost identical to no background !

Project III: Silicon Tracker Alignment system Participants: Tim Blass, Sven Nyberg, Keith Riles, Haijun Yang (University of Michigan) Involvement: Former graduate student (Jin Yamamoto) & Postdoc (Haijun Yang) are putting together a benchtop system. Two undergraduates participate towards senior theses: Tim Blass for Simulation / fitting software, Sven Nyberg for benchtop commissioning Funding: Requested funds in joint UCLC/LCRD proposal (pending), but have begun purchasing equipment for initial bench setup.

Motivation Assumption: Inner detector subject to thermal drifts on time scales too short to collect adequate control sample of tracks for determining alignment from data Conclusion: Need independent alignment system with rapid tracking of drifts “Real time alignment” Goal: Carry out R&D toward a low-mass, real-time tracker alignment system with O(1 micron) precision

Present scope of project • Focusing efforts on Frequency Scanned Interferometer (FSI) [A. F. ~Fox-Murphy et al. , Nuc. Inst. Meth. A 383, 229 (1996)] Basic idea: Measure hundreds of absolute point-to-point distances on tracker structure, using an interferometer “fanout” of optical fibers from a central laser. Laser frequency is scanned and fringes counted for each channel to determine absolute distances. Infer tracker distortions from fit Work Status: identified equipment needed for benchtop demonstration. (Laser choice: New Focus Velocity 6308 – on order (~$20 K) (tunable diode laser, ~670 nm, tuning range ~4. 5 THz) Plan to start commissioning: late April (or May) (one postdoc / two undergraduate students are participating at this point).

Summary & Outlook Ongoing North American projects: - central tracker development based on Silicon Drift - long shaping time readouts for Silicon Strip detectors for central, forward or intermediate tracker - alignment monitoring system for Silicon central tracker - Anticipated projects: - forward tracker, intermediate tracker or TPC envelope based on Si-strip or scintillating fiber (Si. LC coordinates projects between Europe, Asia, and North America) Conclusions: - very promising first ‘wave’ of activity - alternate technologies are being explored (drift, strip) - national labs are drawn in (SLAC, BNL) - R&D funding starts to flow for exploratory 3 -year R&D phase