Programmable System Level Integration on your desktop Atmel’s North America Logic Seminar Series
Facilities and Employees • San Jose, CA (1, 200 employees) – Headquarters, Test and Qualification, R / D • Colorado Springs, CO (1, 900 employees) – Fabrication Assembly & Test, R / D – Two 0. 35 6 inch Wafer Fabs • Rousset, France (600 employees) Total 6, 100 Employees – Fabrication Assembly & Test, R / D – 0. 5 6 inch Wafer Fab and 0. 35 8 inch Wafer Fab • Temic: Heilbronn, Germany (900 Employees) – 0. 5 6 inch Bipolar / Si-Ge Wafer Fab, Assembly, Test, R / D • Temic: Nantes, France (650 employees) – 0. 5 6 inch Wafer Fab, Assembly, Test, R / D • ASIC / ASSP Design Centers – Columbia, MD; Colo. Spgs. ; San Jose; Paris; Munich; Camberley UK; Tokyo; Shanghai; Raleigh, NC; Berkeley, CA; Helsinki; Trondheim – All Facilities Registered ISO 9001 & 9002 • 7 North American & 15 International Sales Offices Slide 2 AT 94 Training 2001
Atmel Product Design Centers Trondheim Helsinki E. Killbride Minneapolis Paris Camberley Dijon Nantes Heilbronn San Jose Chesapeake Portugal Rousset Colo Spgs Raleigh Greece Tokyo Shanghai Hong Kong Malaysia IP Expertise NVM, 8, 16, 32 -bit MCUs, DSP Core, Analog, RF, Rotating Storage, RFID, Data Security Wireless Voice/Data, Image/Sound Processing, Power Measurement, Battery Management, Automotive, Smart Card, TV/Radio, USB, Wired/Wireless L A N, I R D A, Bluetooth Slide 3 AT 94 Training 2001
User-Defined Logic Spectrum Custom ASIC Cell based ASIC Density Gate Array FPSLIC FPGA CPLD PALType ATF 22 V 10 ATF 16 V 8 ATF 20 V 8 Decoders, Glue Logic Slide 4 ATV 2500 B ATF 1500 Fam ATV 750 B State machines, Timing, Control AT 6000 AT 40 K RAM/Logic, Computing, Co-processing AT 94 K ATL 25 Series ATL 35 Series ATL 50 Series ATL 60 Series Macrocells 0. 25, 0. 35, 0. 6 Analog / Digital Programmable High Volume/Low Cost SLI with AVR System Level Integration Analog / Digital/ NV Memory, RF Total Customization Very High Volume AT 94 Training 2001
Atmel’s Flash MCU Families Price vs Performance Engine Control Laser Printer ARM-7 Internet Settop Boxes Disk Drives Cellphones Auto Elect. AVR C 51 Appliances Keyless Entry Price $1 Slide 5 $2 $5 $10 $20 AT 94 Training 2001
SLI Products ASIC – FPGA – Gate Array/ Embedded Array – Cell Based IC – Custom Slide 6 ASSP – – Multimedia Storage Products Smart Cards Wireless Communications – Wireline Communications – Power MCU Microcontrollers – 80 C 51 – AVR™ – ARM™ AT 94 Training 2001
ASSP Multimedia – – – Sound; Dolby AC 3, Voice Recorder and Digital Answering Machine Image Processing; MPEG 2 and Video Conferencing Image Capture Wireline Communications – USB; Function, Host and Hub – Ethernet; 10 T/100 MAC and PHY – Cable Modem; QPSK and QAM Power MCU – Power Meters – Battery Chargers Slide 7 Smart Cards – – Secure Memories Secure Microcontrollers Wireless Communications – Cellular; GSM and CDMA (Baseband) – Networking; Wireless LAN and Bluetooth – RFID; Asset ID and Remote Keyless Entry Storage Products – DVD/CD-ROM – Floppy Disk – Hard Disk AT 94 Training 2001
Fab Processes • • • 0. 6µ CMOS in Production 0. 5µ CMOS in Production 0. 35µ CMOS in Production 0. 25µ CMOS in Production 0. 18µ CMOS in Development • 0. 8µ Bi. CMOS in Production • 0. 6µ Bi. CMOS in Development • 0. 8µ Si-Ge in Production • 0. 35µ Si-Ge Bi. CMOS in Development Slide 8 AT 94 Training 2001
System-On-Chip Issues • $250 K+ NRE • $100 K+ design tools • Large volume requirements • Custom product • Long design time • High risk • IP issues (availability, cost implementation) Clock ASSP Logic FPGA Glue Logic NVM CPU Analogue Power Management Memory SRAM >> System level integration not viable for most customers Slide 9 AT 94 Training 2001
Monolithic SRAM Based FPSLIC Up to 36 K bytes of SRAM 20 MIPS* - 8 bit RISC MCU 8 Bit RISC MCU Configurable SRAM AT 40 K FPGA From 5 K Up to 40 K gates FPGA *30 MIPS version available Q 4 2001 Slide 10 AT 94 Training 2001
FPSLIC Embedded Blocks Configurable SRAM T 4 0 K in te r fa ce SRAM interface AT 40 K FPGA A VR /A 8 Bit RISC MCU • Software configurable interface between blocks already implemented • Pre-implemented Interface blocks save 2000 -5000 FPGA gates Slide 11 AT 94 Training 2001
FPGA Designs Figaro IDS AT 40 K FPGA Development Tools AT 17 • IDS supports Schematic, VHDL or Verilog Design Entry • It generates a BST file for programming the Configurator Slide 12 AT 94 Training 2001
AVR Designs AVR Studio Instruction Set Simulator Requires an Assembly or C Compiler 8 Bit RISC MCU • AVR Studio can be used with Assembly or C to debug code • A HEX file is then used to program the AVR Slide 13 AT 94 Training 2001
FPSLIC Designs Configurable SRAM 8 Bit RISC MCU Slide 14 System Designer for FPSLIC designs includes FPGA and AVR design flows with Co-verification AT 40 K FPGA AT 94 Training 2001
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