Programmable Logic Takes Market Share from Others Total 1996 Market – $9. 5 B Mask Programmed Gate Arrays $5. 6 B Standard Logic $2. 0 B Source: Dataquest, May 1997 Mask Programmed Gate Arrays $7. 4 B 47% 59% 21% Total 2001 Market – $15. 8 B 20% Programmable Logic Share $1. 9 B 16% Standard Logic $2. 6 B 37% Programmable Logic Share $5. 8 B
CMOS Programmable Logic Market Total CMOS Programmable Logic EPLD 1996 $959 SPLD 1996 $411 2001 $279 Source: In-Stat May 1997 FPGA 2001 $2400 1996 $884 CPLD 1996 2001 $548 $2121 CAGR 33% 2001 $2687
ASIC Alternatives Custom Highest Density ASIC Tools Xilinx Product Line Programmable GA Architecture High Density ASIC Tools Programmable AND/OR Architecture Low Density Simple Tools Hard. Wire(TM) Array FPGA EPLD PAL™ Custom Transparent Conversion 100% Tested Programmable PAL Architecture Medium Density PAL-like Tools Gate Array
Company Milestones 1984 1985 1987 1988 1989 1990 1991 1992 1993 1995 opens 1996 1997 1998 Xilinx Founded Introduced first field programmable gate array (FPGA) Introduced second family of FPGAs Established subsidiary in Japan More than one million devices sold Initial public offering Introduced third family of FPGAs Expanded into complex programmable logic (CPLDs) Established Xilinx Hong Kong Xilinx ranked 10 th largest ASIC supplier; Xilinx Ireland Xilinx ranked 8 th largest ASIC supplier Industry’s first advanced 0. 35 & 0. 25 micron FPGAs Introduced low-cost Spartan FPGAs with RAM & cores
Why Xilinx? w Silicon l l Largest, fastest, lowest power FPGAs Lowest cost CPLDs w Software l l l Alliance Series: HDL, synthesis, EDA integration, optimization Foundation Series: ready to use, complete solutions Logi. CORES & Alliance. CORES: optimized and supported w Service l l Most comprehensive field and on-line technical support Advanced Internet Web solutions w Process Technology l l Deep submicron capacity — Sampling 0. 25 micron now Better price, performance, density
Xilinx Revenue Growth 1990– 1998 Fiscal Year Revenues $ Millions $561 $568 $355 $256 $178 $98 $50 Fiscal year ends March 31 $136 $614
High Density FPGA Sales ( ³ 13 K gates, Previous 4 Quarters) 100 Revenue (M$) 80 60 40 20 0 Xilinx Lucent Altera w Xilinx sells more high-density FPGAs than the rest of industry combined. w This is a result of Xilinx’ past and present leadership.
Worldwide Sales Japan Europe 22% 10% Rest of World 5% 63% North America Source: Xilinx
Who’s Using Xilinx Industrial & Networking Military, High Instrumentation Reliability 16% 32% Data Processing Source: Xilinx 12% 4% 1% Misc 35% Communications
Where Xilinx Fits in the Electronics Industry Key components of an electronics system w Processor w Memory w Logic Xilinx is the Leading Innovator of Complete Programmable Logic Solutions
How Customers Use Programmable Logic Xilinx Provides Standard Parts “Blank” Integrated Circuits Customers Create Custom Circuits with Xilinx Software Tools When Design Is Final, Customers Go into Immediate Production
Market Segments w Communications w Computers w Instruments w Medical equipment w Networks w Consumer electronics
Xilinx Application Examples Broadcast Communications Data Communications Military • • • • HDTV CATV (Scramblers & Decoders) Satellite Links Studio Equipment Video Disk Recorder Consumer Digital Audio Decoder Arcade Games Video Games Karaoke Systems Transportation Railway Systems Auto Digital Audio Systems Industrial Test And Measurement Equipment Medical Equipment Motor/Motion Control Semi. Processing Equipment PC Projection Units Robotics ASIC Emulators Postage Systems Vision Systems µP Emulators Lottery Systems Multiplexers Routers Video Conferencing Encryption/Decryption Switches Bridges Modems (incl. PCMCIA) Data Compression LAN Hubs FDDI Wireless LANS (Incl. PCMCIA) Telecommunications • • • • Central Office Switches SONET Interfaces Cellular Base Stations Auto. Directory Assistance Fiber Optic Interfaces ATM ISDN Interfaces Voice-Mail Controllers PBX Equipment T 1 Multiplexers Speech Synthesis Pay Phone Control Data Compression Computer And Communications Systems Missile Guidance Avionics Fire Control Computer • • Memory Interfaces DMA Controllers Local And Mezzanine Bus Interfaces Cache Controllers SSP Co-Processors Multi-Media Graphics Peripherals • • • • Disk Controllers Video Controllers FAX (Incl. PCMCIA) Barcode Readers Teller Machines Tape Controllers Sound Cards Modems (Incl. PCMCIA) POS Systems Data Acquisition Cards Terminals Printers Scanners Copiers
Strategic Business Model Ensures Focus w “Fabless” strategy l l l Leading edge IC process technology Wafer capacity at competitive prices Fastest, lowest cost, densest parts w Independent sales organization l l Sales is a variable cost Permits greater reach—over 15, 000 customers w Focus on key strengths l l l Research and development Marketing Applications engineering
Xilinx’ Fabless Advantage w $136 M equity investment in UMC l guaranteed 33% capacity of new 8” fab w $300 M advanced payment to Seiko l guaranteed capacity for next 5 years w Access to 0. 25 & 0. 18 leading edge fab in 1997 w Guaranteed fab access to support $2 B/year revenue w 50 engineers working in-house on process technology l Developed Fast. FLASH process
Process Technology Leadership Roadmap Feature Size (µm) 5 V “cost reduction line” has been valid for >10 years 5. 0 V 3. 3 V 2. 5 V 1. 8 V Year
Density Roadmap 12 M 2. 0 M gates 100, 000 1. 2 M 10, 000 120 K 1, 000 1994 Year 1996 1998 Gates Density (logic cells) 1, 000 12 K 2000 2002 Year w 2001 -> 150, 000 logic cells (2. 0 M gates) w logic cell = 4 -input LUT + FF
Xilinx vs Other FPGA Interconnect Technology Xilinx Interconnect Other FPGA Interconnect Across Chip Logic Block 1 Logic Block 2 1 x Logic Block 3 . . . Logic Block n Logic Block 1 1 x . . . Logic Block 2 Logic Block n 4 x 4 x 3 x 1 x 4 x 6 x Logic Block (next row) “Segmented” Interconnect Lines “Non-Segmented” Interconnect Lines • Variable Length Interconnect Lines • 1 Segmented line required to connect 4 logic cells • Smaller Die Size => Lower Cost • Fixed Length Interconnect Lines • 3 Single Signal lines required to connect 4 logic cells • Larger Die Size => Higher Cost Segmented Interconnect Structure Provides Faster Logic Cell Connections
MHz 1/(Tsetup+Tclock-to-out) System Clock Rate Performance Roadmap 200 180 160 140 120 100 80 60 40 20 0 1995 1996 1997 1998 1999 2000 Year w Process Technology Makes this Possible w 5 x Improvement in 5 years
Power Roadmap (for constant gates & frequency) w Power CV 2 f w Low power = high performance 3 x Power w Low power = higher non-segmented reliability interconnect (others) >>3 x segmented interconnect (Xilinx) 1996 Year 2001
Hardwire for High Volume 2001 w Same curves, change numbers $ w Largest savings on biggest devices FPGA w Design Once w Risk-free migration Hard. Wire w No test vectors 20 k 40 k 60 k 80 k 100 k Logic Cells 250 k 500 k 750 k 1 M 1. 25 M Gates
Xilinx Pioneers FPGA Packages Package Pins 3000 PQFPs & VQFPs BGA 1000 Flip-chip SBGA 100 1992 1994 1996 1998 2000 2002 Year w First to use PQFP & VQFP w First to use BGA & SBGA (Super BGA) w Investigating flip-chip today for higher integration
Availability of Logi. Cores 1997 1998 Buses PCI slave 33 MHz PCI 3. 3 v slave PCI slave 66 MHz PCI master 33 MHz PCI 3. 3 v master PCI master 66 MHz USB device controller ISABus Plug & Play Telecom ATM cell delineation E 1/E 2/E 3 framer SONET standard cores ATM Utopia master E 1/E 2/E 3 processor OC standard cores ATM Utopia slave E 1 crossconnect Echo canceller ISDN, HDLC controller E 1 Add/drop mux ADSL M 16450 UART SONET/SDH pointer Ethernet STS-3 parallel framer QAM/FEC DSP FIR filters Convolution filters Math toolkit Correlators (8 -128 bits) Channel models Voice models Multipliers, high speed MPEG RZ 1000 DFT MAC Xilinx is the leader in Basic Blocks 8237 DMA controller Logi. Cores today libraries ASIC 8254 interval controller 8032
Xilinx FPGA Architectures 1997 1998 1999 w 11, 000 Logic Cells (125 k gates) w 32, 000 Logic Cells (400 k gates) w 65, 000 Logic Cells (800 k gates) w fastest RAM w programmable IOs w 5 volt tolerant IOs w Advanced Clocking w D/A & A/D support w custom cores w 100 MHz system w buffered quad line speed w Versa. Ring IOs w fast re-configure w 6 ns pin-to-pin w hierarchical memory solution w efficient segmented routing w built-in logic analyzer w high speed differential interface (500 MHz)
Xilinx Leads - Others Follow Lucent Altera FPGA Solution 1985 1990 1994 Pin Compatibility 1988 1990 1996 Hardwire 1990 ? ? On-chip RAM 1991 1993 1996 FPGAs >= 20 k gates 1994 1995 1996 Synopsys 5 Year Relationship FPGA Cores 1994 ? 1996 1995 ? ? Shipped 40, 000 th FPGA 1996 ? ? Xilinx has a long history of leadership. This trend will continue!!
A History of Software Innovation Xilinx Innovation 1985 Industry’s First FPGA Design Tools XACTTM 1985 Industry’s First Timing-Driven Tools FPGA Specific-Timing Analysis PARTM 1992 Timing Graphical Editor for Programmable ICs Wizard. TM 1992 EPICTM Lucent 1990 1986 1992 1993 1994 1992 TM XBLOX , Logi. BLOX Automatic Module Generation Software Architectural Modeling Commitment To Open Systems 1992 FPGA Architect. TM 1990 Xilinx 1992 Synopsys Constraint Interpretation HLDLTM Synopsys Technology Partnership Graphical Hardware Debugging Alliance. TM 1994 1990 Hardware Debugger. TM Software Internationalization 1996 Fully Verified and Optimized IP Cores 1996 Logi. Cores. TM Altera No Answer 1994 1995 1994 No Answer 1994 Q 4’ 96 No Answer No Answer
Overview the FPGA Basic Architecture
PLD Advantages Vs Gate Array w Faster Time to Market l l l Immediate Prototypes Faster Debug Lower Risk PCB Development w Faster Access to Hardware for Firmware/Software Development w Test Marketing Capability w Field Upgrade Potential w Solve Gate Array Obsolescence Problems
CPLDs and FPGAs CPLD Complex Programmable Logic Device FPGA Field-Programmable Gate Array Architecture PAL-like Gate array-like Density Low-to-medium Medium-to-high Basic Cell Product Term CLB & LUT Application Combination based Register Based Performance Predictable timing Application dependent Design Entry Equation & Schematic & HDL
What is the FPGA I/O Blocks (IOBs) Configurable Logic Blocks (CLBs) Programmable Interconnect - Look up table base architecture - Rich Flip Flop application design - No predictable pin to pin delay just CLB delay - One hot decoding & Reconfiguration - Lower price per gate & High density and Speed
I/O Block (IOB) w Identical I/O Blocks line the periphery of die l l Input, output, or bi-directional Registered, latched, or combinatorial Three-state output Programmable output slew rate
IOB Primitives w User explicitly defines what resources in the IOB are to be used l l l Special IOB primitives Inverters may also be pulled into IOBs Properties attached to primitives IPAD IBUF OBUF Input IOB OPAD Output IOB
Use Pull-ups/Pull-downs to Prevent Floating w Pull-up automatically connected on unused IOBs w Outputs of unused IOBs are automatically disabled w A PULLUP or PULLDOWN primitive can be specified on used IOBs l Must be instantiated in HDL w Inputs should not be left floating l Add a pull-up to design inputs that may be left floating to reduce power and noise
Slew Rate Control w Slew rate controls output speed w Default slow slew rate reduces noise w Use fast slew rate wherever speed is important l FAST parameter on output logic primitive FAST OPAD OBUF
Use I/O Registers w Guaranteed clock to out and clock to setup See Data Book (Pin-to-Pin Input Parameter Guidelines) l w Provides fastest SYSTEM speed l Note: Will not be reported by the static timing analysis tool. . From: FPGA D Q CE Into: FPGA Q CE D I/O pad
CLB (Configurable Logic Block) w 2 4 -input LUTs and 1 3 -input LUT l ” muxes feed F/G LUTs or independent inputs to H LUT w 2 edge-triggered FFs l l l DIN EC SR w 4 outputs l Fed by “B” muxes
Flip-Flops in the CLB w 2 Edge-triggered flip-flop per CLB w Independent Clock polarity w Selectable clock enable w Asynchronous set or reset l Local and/or global control
Combination Logic Resources w Lookup tables l l Can be combined into multiple levels Special cascade chain in XC 5000 w Carry logic l XC 4000 E/X/XC 5000 w Wide decoders l XC 4000 E/X w Three-state buffers l XC 4000 E/X/XC 5000
FPGA Lookup Tables w Two four-input functions and one three-input function w One five-input function w One four-input function and some six-input functions C 1 -C 4 w Some nine-input functions DIN S/R F 1 -F 4 H 1 F H G 1 -G 4 G to flip-flops & CLB outputs
Look-Up Tables w Combinatorial Logic is stored in Lookup Tables (LUTs) in a CLB w Example: Combinatorial Logic A B Z C D • Capacity is limited by number of inputs, not complexity • Delay through CLB is constant A 0 0 0 B 0 0 1 1 C 0 0 1 1 0 0 D 0 1 0 1 Z 0 0 0 1 1 1 . . . 1 1 1 1 0 0 1 1 0 1 0 0 0 1
TM XC 4000 Select-RAM Advantages q Select the Function - Can be Single or Dual Port - Synchronous or Asynchronous - “Mix and match” q Select the Size - No wasted resources - Scalable to needed size q Select the Location - Can be located anywhere on die - Adjacent to critical circuits for speed q. Select the Programming Method - Via bitstream on start-up - During design operation q. Simple to use Data Address WE Clock XC 4000 E RAM Data 2 Address 2 Optional Dual Port
ROM is Equivalent to Logic w When using ROM, it is simply defining logic functions in a look-up table format l Memory might be an easier way to define logic w FPGA lookup tables are essentially blocks of RAM l l Data is written during configuration Data is read after configuration – As Gates Effectively operate as a ROM I 1 I 2 F 1 F 2 O = I 1*I 2 A 0 X O A 1 F 2 As ROM DATA(0)=0 DATA(1)=0 X DATA(2)=0 DATA(3)=1 DOUT
RAM Provide 16 X Flip-Flops w 32 bits vs. 2 bits of storage w Non-simultaneous access CLB D 1 A 0 A 1 A 2 A 3 A 4 CLB D 1 WE Q 1 D 2 32 bits D Q Q 2 O 1 CLK w 32 x 8 shift register with RAM = 11 CLBs l Using flip-flops, takes 128 CLBs for data alone
RAM for Status registers w Provides up to a 16 to 1 density increase! w Easier routing for FPGA w Ten 16 bit read/write status registers on a bus use: 160 registers -or- 80 CLBs w In RAM the same ten status registers use: 16 four input look-up-tables -or- 8 CLBs Reg. Vs. RAM
16 x 32 FIFO Uses Only 32 CLBs with RAM w If implemented in registers: l 256 CLBs for storage alone w Implemented in XC 4000/SPARTAN RAM: l Storage requires only one CLB per 32 bits – Other CLBs used for addressing and control l Runs at 66 MHz in XC 4000 XL-2
Dual-Port RAM w One common synchronous write port w Two asynchronous read ports w 16 x 1 max per CLB
Fast Memory: Dual-Port RAM Mhz 70 XC 4000 E Select-RAM 65 60 Altera’s Bottleneck = One Port 55 50 Data In Over 2 x Faster System Performance 45 0100111011 01001 40 Data Out 35 110110101001 0 1 0 Block RAM Emulated Dual Port 30 FLEX EAB 25 20 110110101001 1 0 01001 FLEX Block RAM is Single-Port only. Must emulate Dual-Port cutting performance in half. 8 Bit 16 Bit 32 Bit Data Bus Size Xilinx Select-RAM delivers 2 x performance for large Dual-Port RAM Average pin to pin performance of dual port RAM with various depth from 8 to 1024 words
Higher Utilization: Dual-Port RAM FLEX 10 K Dual-Port Emulation Logic XC 4000 E/EX LC LC LC LC LC LC LC LC LC LC 16 x 4 Dual. Port RAM EAB 16 x 4 Dual Port RAM 30 Logic Cells PLUS 1 EAB 10 Logic Cells FLEX 10 K emulation logic for small Dual-Port RAM consumes more logic cells than complete Xilinx solution
Programmable Interconnect w Resources to create arbitrary interconnection networks CLB w Various types of interconnect l l CLB Switch Matrix Flexible general-purpose interconnect Low-skew long lines w Internal three-state buffers for buses and wide functions CLB
Interconnect Hierarchy
Global Clock Buffers w Clock Buffers are low-skew, high drive buffers Also known as Global Buffers l Drive low-skew, high-speed long line resources l Drive all Flip-Flops and Latches in FPGA l Can also be used for high-fanout signals l Eight global buffers per FPGA l w Additional clocks and high fanout signals can be routed on long lines l Otherwise routed on general interconnect – Slower and higher skew
Use Global Clock Buffers w Use clock buffers for highest fanout clocks l l Drive low-skew, high-speed long line resources Use BUFG primitive to be family-independent w Limit number of clocks to ease placement issues l l l XC 4000 E: 8 XC 4000 X : 20 XC 5000: 4 w Additional clocks might be routable on long lines l l Otherwise routed on general interconnect D Slower and. IPAD higher skew BUFGS
Use Extra Global Buffers w Do you have high fan-out Clock Enables, or IOB Tristates? w Drive them through a unused BUFG to lower skew and higher performance w BUFGs have less than 1 ns Skew to clock and CE inputs w Have to instantiate in HDL for non-clock signals INPUT CE or OE P D Q CE BUFG CLOCK R
Global Buffers Interconnect w Flexibility on BUFGS allows any four of the eight to be available in any column w All connect to clock pins, but only some connect to some of the other pins
How to use to Xilinx Foundation Tool
Integration of All Tools • Hierarchy Browser allows for direct access to these files • Message Window provides error and status messages • Toolbar • Project Flowchart provides automate d data transfer
Library Manager w The command File>Project Libraries enables the user to associate other project libraries w To open the Library Manager, click on its icon w The Library Manager organizes all macros into libraries and enables the user to delete, copy,
Some Useful Commands w Use the command File>Copy Project to copy an entire Foundation project directory w Use the command File>Project Type to change the design family in one step
Adding Symbols • To start the Schematic Editor, click on its icon • Select-and-Drag mode enables moving symbols, wires, and busses throughout the work area • To add symbols to the schematic click on the Symbol Toolbox icon • Scroll through the list to find a particular symbol, or enter it’s name at the bottom of the SC Symbols box • Replicate symbols by clicking on the symbol while the Symbols Toolbox is still active
Wires and Buses w To draw wires, click on the Draw Wires icon and click on the two endpoints w To draw buses, click on the Draw Buses icon and click on the two endpoints w To name a bus, double click on the bus and enter the bus name and width w To name a wire, double click on the wire and enter the
Drawing Bus Taps w Extend the bus vertically so there will be sufficient room w Terminate the bus by double-clicking the right mouse button w Name the bus w Click on the bus taps icon w Click on the bus name (in green) w Place the taps by clicking on each of the destinations starting with the least significant bit
Query/Find Window w Query lets the user scan through the schematic to determine connections w Select a symbol or wire in the schematic, and click on the Query Mode icon w This is useful when connecting or disconnecting symbols w The Find function helps the user locate signals, chips, and pins w Find is useful when looking for objects reported by the Alliance M 1 Software
Adding Hierarchy w Tie the project together with a toplevel schematic that includes macros from all the Foundation Design Entry Tools w As each element of the project is created, make a symbol to represent the macro so that it can be added to the top-level schematic w Before a symbol can be created to represent a schematic macro, the macro must contain I/O Terminals that represent ports on the symbol w To enter an I/O Terminal, click on its icon, enter the terminal name, select the type of port, place it, and wire it up.
Entering a Level of Hierarchy w To enter a lower level of hierarchy, click on the Hierarchy Push/Pop icon and double click on the symbol w To go back to a higher level of hierarchy, double-click on a blank area of the sheet. w To create a symbol for a schematic with I/O terminals, use the command: Hierarchy>Create Macro Symbol From Current Sheet w This will place a symbol in the project library so it can be added to the top-level schematic
Symbol Properties w Attributes and parameters communicate necessary information to the Alliance M 1 Software w Attributes and parameters are maintained in the Symbol Properties dialog box w Double-click on a symbol to enter the Symbol Properties dialog box w To make a pin assignment, double-click on the OPAD symbol, enter “LOC” in the name box and enter P 49 in the description box
Symbol Editor w To edit a symbol, click on the Symbol Editor button inside the Symbol Properties dialog box w The Symbol Editor can be used to move ports around on a symbol so the schematic looks good
Importing Viewlogic Schematics w Viewlogic schematics can be imported into the Foundation schematic editor by using the command File>Import Viewlogic Schematic from the Schematic Editor w Some properties of the schematic can be modified w Importing a Viewlogic Schematic can maintain hierarchy and many of the schematics characteristics
Some Useful Commands w Add VCC and GND symbols by using the SC Symbols box w Sheet size can be changed by using the menu command File>Page Setup w To modify the grid, text, and colors use the menu command View>Preferences w Edit the Table printed at the bottom of every schematic page by using the menu command File>Table Setup w Zoom in, out, area, and to page by using their icons
Logi. BLOX w Logi. BLOX is a graphical interactive tool for creating high-level modules w Logi. BLOX customizes components w The GUI disables selections that are incompatible with your design selections w Logi. BLOX components are entered just like a macro w Functional simulation is possible without implementation w XC 4000 E/XL/XL support
Module Types • • Clock Dividers Comparators Data Registers Inputs/Outpu ts Memories Shift Registers Simple Gates Tristate Buffers • Adders • Subtracte rs • Counters • Constants • Pads • Multiplexe rs • Decoders
Counters w Choosing a style will determine the resources used for the module w For example, choosing the Maximum Speed option tells the software to use the Carry Logic resources if an XC 4000 EX FPGA has been selected w The Counters module
Adder/Subtracters w All arithmetic functions can utilize the Carry Logic resources w Adders/Subtracter s, Accumulators, and the Comparators modules can be customized for signed/unsigned binary
Memories w The Memories module is useful for creating custom sized RAM, ROM, or dual-port RAM w This module will create the input decoder and output multiplexer when necessary w Specify the necessary bus width and memory depth to customize the size w Enter a memory filename to initialize a memory (for example,
Multiplexers w The Multiplexer module can have up to eight input buses w This module can be optimized for area and speed w The Mux module can utilize the tristate buffers by selecting the Wired-AND Style
Tri-state Buffers w This module synthesizes internal non-inverting tri-state buffers w The output enable is active-low w If an inversion is necessary add an inverter to the output enable w One or two pull-up resistors can be used to get faster transition times
Inputs/Outputs w The Inputs/Outputs module represents the I/O block associated with each pin on a device w Using this module allows customizable bus widths and the use of the IOB register w Buffers can be bidirectional, latched, or registered
Pads w The Pads module represents the actual pins of a device w Location constraints can be entered for each element of a bus w The slew rate is set low by default to minimize power transients w The Delay attribute can provide 0 ns hold time at the IOB register w The Pull-up/down attribute is used to
Waveform Viewer w To open the Simulator, click on the Functional Simulator or the Timing Simulator icons w An implementation within the Alliance M 1 software must be completed before a Timing Simulation can be completed w Contains a list of input and output nodes and an area for viewing the signals generated by the simulator
Inserting Probes w Add probes in the schematic to automatically load a node into the Waveform Viewer w Click on the Probes icon and click on each node name in the schematic w The probes change color in the schematic to reflect their state
Component Selector w Alternatively, open the Waveform Viewer, and enter nodes by using the Component Selector w Open the Component Selector by clicking on its icon in the Waveform Viewer
Stimulator Selector w Bc and NBc represent the normal and inverted outputs of a 16 -bit counter w The square LEDs represent 16 user-defined formulas w The buttons labeled C 1 - C 4 represent user-defined clocks w The CS button is used with the graphical waveform editor to create a custom signal w To modify the clock frequency of the 16 -bit counter, use the command
Simulator Toolbox w Once the necessary signals have been inserted, the Step and Long buttons can be used to control the amount of time to simulate w The Forward and Reverse buttons are used to scan the waveforms for a particular event w The Power on Reset button moves the selector to the
Displaying Buses w To group signals, click on the MSB, hold the shift key, and click on the LSB. Then use the menu command Signal>Bus>Combine w To ungroup a bus, select the bus and use the menu command Signal>Bus>Flatten w To change the bus format, select the bus then use the menu command Signal>Bus>Display… w Any signals can be
Some Useful Commands w To save simulation vectors, use the menu command File>Save Simulation State w To clear the waveform area, move the blue line to the beginning of the area to be deleted and use the menu command Waveform>Delete>All Waveforms after Cursor w To clear all waveforms in the viewer, click on the Delete Waveforms icon w To load a Viewlogic command file, use the command File>Run Script File
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