Скачать презентацию Paul Scherrer Institute Stefan Ritt Applications and future Скачать презентацию Paul Scherrer Institute Stefan Ritt Applications and future

d37b6059ef3773674cffdd578ee32c19.ppt

  • Количество слайдов: 40

Paul Scherrer Institute Stefan Ritt Applications and future of Switched Capacitor Arrays (SCA) for Paul Scherrer Institute Stefan Ritt Applications and future of Switched Capacitor Arrays (SCA) for ultrafast waveform digitizing

Why do we need ultrafast waveform digitizing? Pulse shape discrimination Detector Rise time < Why do we need ultrafast waveform digitizing? Pulse shape discrimination Detector Rise time < 1 ns Ultra-precise timing < 10 ps Stefan Ritt Pile-up recognition 2/30

Can it be done with FADCs? • • 8 bits – 3 GS/s – Can it be done with FADCs? • • 8 bits – 3 GS/s – 1. 9 W 10 bits – 3 GS/s – 3. 6 W 12 bits – 3. 6 GS/s – 3. 9 W 14 bits – 0. 4 GS/s – 2. 5 W 24 Gbits/s 30 Gbits/s 43. 2 Gbits/s 5. 6 Gbits/s PX 1500 -4: 2 Channel 3 GS/s 8 bits l 24 x 1. 8 Gbits/s 0 1 1 - 1. 8 GHz! • Requires high-end FPGA • Complex board design • FPGA power Stefan Ritt €/ k e nn a ch ADC 12 D 1 X 00 RB: 1 Channel 1. 8 GS/s 12 bits 3/30

Overview • Design Principles and Limitations of Switched Capacitor Arrays (SCA) IN Out Clock Overview • Design Principles and Limitations of Switched Capacitor Arrays (SCA) IN Out Clock • Overview of Chips and Applications input shift register • Future Design Directions. . . . Stefan Ritt 4/30

Switched Capacitor Array (Analog Memory) 10 -100 m. W 0. 2 -2 ns Inverter Switched Capacitor Array (Analog Memory) 10 -100 m. W 0. 2 -2 ns Inverter “Domino” ring chain IN Waveform stored Clock Shift Register Out FADC 33 MHz “Time stretcher” GHz MHz Stefan Ritt 5/30

Digitizing only short time windows Trigger sampling Stefan Ritt low power digitization sampling digitization Digitizing only short time windows Trigger sampling Stefan Ritt low power digitization sampling digitization Trigger high power 6/30

Time Stretch Ratio (TSR) Typical values: dts IN Clock • dts = 0. 5 Time Stretch Ratio (TSR) Typical values: dts IN Clock • dts = 0. 5 ns (2 GSPS) • dtd = 30 ns (33 MHz) → TSR = 60 Out Dead time = Sampling Window ∙ TSR (e. g. 100 ns ∙ 60 = 6 ms) Stefan Ritt dtd 7/30

How to measure best timing? Simulation of MCP with realistic noise and different discriminators How to measure best timing? Simulation of MCP with realistic noise and different discriminators J. -F. Genat et al. , ar. Xiv: 0810. 5590 (2008) Stefan Ritt Beam measurement at SLAC & Fermilab D. Breton et al. , NIM A 629, 123 (2011) 8/30

How is timing resolution affected? voltage noise Du signal height U timing uncertainty Dt How is timing resolution affected? voltage noise Du signal height U timing uncertainty Dt rise time tr number of samples on slope Stefan Ritt Simplified estimation! 9/30

How is timing resolution affected? Assumes zero aperture jitter U today: optimized SNR: next How is timing resolution affected? Assumes zero aperture jitter U today: optimized SNR: next generation: Du fs f 3 db Dt 100 m. V 1 m. V 2 GSPS 300 MHz ∼ 10 ps 1 V 1 m. V 2 GSPS 300 MHz 1 ps 100 m. V 10 GSPS 3 GHz 1 ps includes detector noise in the frequency region of the rise time and aperture jitter Stefan Ritt 10/30

Limits on analog bandwidth • External sources • Detector • Cable • Connectors • Limits on analog bandwidth • External sources • Detector • Cable • Connectors • PCB • Preamplifier • Internal sources • Bond wire • Input bus • Write switch • Storage cap Low pass filter PCB Chip Det. Cpar Stefan Ritt 11/30

Timing Nonlinearity • Bin-to-bin variation: “differential timing nonlinearity” • Difference along the whole chip: Timing Nonlinearity • Bin-to-bin variation: “differential timing nonlinearity” • Difference along the whole chip: “integral timing nonlinearity” • Nonlinearity comes from size (doping) of inverters and is stable over time → can be calibrated • Residual random jitter: <4 ps RMS exceeds best TDC Dt Dt Dt RMS = 3. 19 ps D. Stricker-Shaver, private communication Stefan Ritt 12/30

Synchronization Master clock 20 MHz PLL Trigger ADC Stefan Ritt MEG @ PSI: 40 Synchronization Master clock 20 MHz PLL Trigger ADC Stefan Ritt MEG @ PSI: 40 ps over 3000 channels 13/30

Part 2 • Design Principles and Limitations IN Out Clock • Overview of Chips Part 2 • Design Principles and Limitations IN Out Clock • Overview of Chips and Applications input shift register • Future Design Directions. . . . Stefan Ritt 14/30

Design Options • • CMOS process (typically 0. 35 … 0. 13 mm) sampling Design Options • • CMOS process (typically 0. 35 … 0. 13 mm) sampling speed Number of channels, sampling depth, differential input PLL for frequency stabilization Input buffer or passive input Analog output or (Wilkinson) ADC Internal trigger Exact design of sampling cell PLL Trigger ADC Stefan Ritt 15/30

Switched Capacitor Arrays for Particle Physics E. Delagnes D. Breton CEA Saclay G. Varner, Switched Capacitor Arrays for Particle Physics E. Delagnes D. Breton CEA Saclay G. Varner, Univ. of Hawaii STRAW 3 LABRADOR 3 TARGET AFTER SAM NECTAR 0 • 0. 25 mm TSMC • Many chips for different projects (Belle, Anita, Ice. Cube …) • 0. 35 mm AMS • T 2 K TPC, Antares, Hess 2, CTA www. phys. hawaii. edu/~idlab/ matacq. free. fr DRS 1 DRS 2 DRS 3 DRS 4 2002 2004 2007 2008 Stefan Ritt • 0. 25 mm UMC • Universal chip for many applications • MEG experiment, MAGIC, Veritas, TOF-PET H. Frisch et al. , Univ. Chicago PSEC 1 - PSEC 4 • 0. 13 mm IBM • Large Area Picosecond Photo-Detectors Project (LAPPD) psec. uchicago. edu SR R. Dinapoli PSI, Switzerland drs. web. psi. ch 16/30

MEG On-line waveform display “virtual oscilloscope” g S 848 PMTs template fit Liq. Xe MEG On-line waveform display “virtual oscilloscope” g S 848 PMTs template fit Liq. Xe m PMT 1. 5 m m+ e+g At 10 -13 level 3000 Channels Digitized with DRS 4 chips at 1. 6 GSPS Stefan Ritt Drawback: 400 TB data/year 17/30

Pulse shape discrimination g m g a a Discovered offline ! Stefan Ritt m Pulse shape discrimination g m g a a Discovered offline ! Stefan Ritt m 18/30

Other Applications Gamma-ray astronomy CTA 320 ps Magic Antares (Mediterranian) Antarctic Impulsive Transient Antenna Other Applications Gamma-ray astronomy CTA 320 ps Magic Antares (Mediterranian) Antarctic Impulsive Transient Antenna (ANITA) Ice. Cube (Antarctica) To. F PET (Siemens) Stefan Ritt 19/30

Things you can buy and make • • • DRS 4 chip (PSI) 32+2 Things you can buy and make • • • DRS 4 chip (PSI) 32+2 channels 12 bit 5 GSPS > 500 MHz analog BW 1024 sample points/chn. 110 ms dead time • • M. Hori (CERN) DRS 4 chip 8 channels LVDS links • • • Stefan Ritt SAM Chip (CEA/IN 2 PD) 2 channels 12 bit 3. 2 GSPS 300 MHz analog BW 256 sample points/chn. On-board spectroscopy DRS 4 Evaluation Board 4 channels 12 bit 5 GSPS 750 MHz analog BW 1024 sample points/chn. 500 events/sec over USB 2. 0 20/30

The smallest DAQ system Raspberry Pi 50 EUR, 3. 5 W DRS 4 Evaluation The smallest DAQ system Raspberry Pi 50 EUR, 3. 5 W DRS 4 Evaluation Board 900 EUR, 2. 5 W Idea: Martin Brückner HU Berlin for Hi. SCORE Stefan Ritt 21/30

Part 3 • Design Principles and Limitations IN Out Clock • Overview of Chips Part 3 • Design Principles and Limitations IN Out Clock • Overview of Chips and Applications input shift register • Future Design Directions. . . . Stefan Ritt 22/30

Next Generation SCA Short sampling depth • Low parasitic input How capacitance Deep sampling Next Generation SCA Short sampling depth • Low parasitic input How capacitance Deep sampling depth • Digitize long waveforms to combine best of both worlds? • Accommodate long • Wide input bus • Low Ron write switches High bandwidth Stefan Ritt trigger delay • Faster sampling speed for a given trigger latency 23/30

Cascaded Switched Capacitor Arrays shift register input • 32 fast sampling cells (10 GSPS) Cascaded Switched Capacitor Arrays shift register input • 32 fast sampling cells (10 GSPS) → small capacitance, high bandwidth • 100 ps sample time, 3. 1 ns hold time • Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) • Shift register gets clocked by inverter chain from fast sampling stage . . . . fast sampling stage Stefan Ritt secondary sampling stage 24/30

The dead-time problem sampling digitization Sampling Windows * TSR lost events Only short segments The dead-time problem sampling digitization Sampling Windows * TSR lost events Only short segments of waveform are of interest Stefan Ritt 25/30

digitization FIFO-type analog sampler • • Samples are digitized asynchronously • “De-randomization” of data digitization FIFO-type analog sampler • • Samples are digitized asynchronously • “De-randomization” of data • Can work dead-time less up to average rate = 1/(window size * TSR) • Stefan Ritt FIFO sampler becomes immediately active after hit Example: 2 GSPS, 10 ns window size, TSR = 60 → rate up to 1. 6 MHz 26/30

Plans DRS 5 (PSI) • Self-trigger writing of 128 short 32 -bin segments (4096 Plans DRS 5 (PSI) • Self-trigger writing of 128 short 32 -bin segments (4096 bins total) • Storage of 128 events • Accommodate long trigger latencies • Quasi dead time-free up to a few MHz, • Possibility to skip segments → second level trigger • Attractive replacement for CFG+TDC • First version planned for 2014 CEA/Saclay • Dual gain channels • Dynamic power management (Read/Write parts) • Region-of-interest readout Stefan Ritt 27/30

m + → e + e -e + • Mu 3 e experiment planned m + → e + e -e + • Mu 3 e experiment planned at PSI with a sensitivity of 10 -16 • 2*109 m stops/sec • Scintillating fibres & tiles • 100 ps timing resolution • 2 -3 MHz hit rate • Can only be done with DRS 5! Stefan Ritt 28/30

DRS 4 Usage ity un de i dw rl o m om C W DRS 4 Usage ity un de i dw rl o m om C W http: //drs. web. psi. ch Stefan Ritt 29/30

Conclusions • SCA technology offers tremendous opportunities • Several chips and boards are on Conclusions • SCA technology offers tremendous opportunities • Several chips and boards are on the market for evaluation • New series of chips on the horizon might change frontend electronics significantly Stefan Ritt 30/30

Stefan Ritt 31/30 Stefan Ritt 31/30

Wave. DREAM board • • • 16 channels standalone (GBit Ethernet) or 3 HE Wave. DREAM board • • • 16 channels standalone (GBit Ethernet) or 3 HE crate (256 channels) Variable gain 0. 1/1/10 or 1/10/100 Flexible integrated triggering Global clock synchronization Integrated Si. PM biasing (up to 200 V) Currently under development at PSI Stefan Ritt 32/30

Wave. DREAM analog front-end switchable HV biasing Attenuator Gain 2 -10 Coupling Gain 10 Wave. DREAM analog front-end switchable HV biasing Attenuator Gain 2 -10 Coupling Gain 10 AC/DC/Calib Gain Selector Differential Driver Trigger Stefan Ritt 33/30

Si. PM High Voltage on Wave. DREAM board • • • Whole circuit works Si. PM High Voltage on Wave. DREAM board • • • Whole circuit works on virtual +68 V gound Connectors can stay on ground Regulation +68 V … +73 V Current sense ~1 n. A resolution ADC/DAC: ~8 EUR/channel Common DC-DC converter: +1 EUR / channel (Commercial or Cockroft-Walton) Stefan Ritt 34/30

Crate backplane & Clock distribution • Star connectivity for • GTP • SERDES • Crate backplane & Clock distribution • Star connectivity for • GTP • SERDES • Slave Select • Bus connectivity for • SPI (except SS) • MISC • Clock • Trigger Stefan Ritt 35/30

Digital Pulse Processing (DPP) C. Tintori (CAEN) V. Jordanov et al. , NIM A Digital Pulse Processing (DPP) C. Tintori (CAEN) V. Jordanov et al. , NIM A 353, 261 (1994) Stefan Ritt 36/30

Template Fit • Determine “standard” PMT pulse by averaging over many events “Template” • Template Fit • Determine “standard” PMT pulse by averaging over many events “Template” • Find hit in waveform • Shift (“TDC”) and scale (“ADC”) template to hit • Minimize c 2 • Compare fit with waveform • Repeat if above threshold • Store ADC & TDC values pb Experiment 500 MHz sampling 14 bit 60 MHz www. southerninnovation. com Stefan Ritt 37/30

Some specialities • LAB Chip Family (G. Varner) • Deep buffer (BLAB Chip: 64 Some specialities • LAB Chip Family (G. Varner) • Deep buffer (BLAB Chip: 64 k) • Double buffer readout (LAB 4) • Wilkinson ADC 6 mm 16 mm • NECTAR 0 Chip (E. Delagnes) • Matrix layout (short inverter chain) • Input buffer (300 -400 MHz) • Large storage cell (>12 bit SNR) • 20 MHz pipeline ADC on chip p Wilkinson-ADC: • PSEC 4 Chip (E. Oberla, H. Grabas) • 15 GSPS • 1. 6 GHz BW @ 256 cells • Wilkinson ADC Stefan Ritt Cell contents Ram measure time 38/30

How to fix timing nonlinearity? • LAB 4 Chip (G. Varner) uses “Trim bits” How to fix timing nonlinearity? • LAB 4 Chip (G. Varner) uses “Trim bits” to equalize inverter delays to < 10 ps • Dual-buffer readout for decreased dead time • Wilkinson ADCs on chip First tests will be reported on RT 12 conference June 11 -15, Berkeley, CA Stefan Ritt 39/30

DRS 5 -T 1 • First silicon in 110 nm technology • Implemented just DRS 5 -T 1 • First silicon in 110 nm technology • Implemented just inverter chain with 32 cells • 4 m. A @ 10 GSPS at 1. 4 V PLL Trigger ADC Stefan Ritt 40/30