Particles and Fields Package PFP SWEA Pre-CDR Peer

Particles and Fields Package (PFP) SWEA Pre-CDR Peer Review Ellen Taylor Space Science Laboratory, UCB SWEA Pre-CDR Peer Review 1

Outline • • Overview (Block Diagram) Requirements Interfaces Digital Board EM Status LVPS Board EM Status Resources Schedule and Parts Status SWEA Pre-CDR Peer Review 2

CESR / UCB-SSL Collaboration IRAP/CESR, Toulouse • • Analyzer MCP Anode HVPS SSL, Berkeley • Pedestal • Digital / FPGA • LVPS (same as for STEREO SWEA) SWEA Pre-CDR Peer Review 3

SWEA Electrical Team – SSL • • David L. Mitchell (Instrument Lead) Ellen Taylor (Digital Electronics) Dorothy Gordon (FPGA) Peter Harvey (FSW [PFDPU]) Peter Berg, Selda Heavner (Power Supplies) Dave Curtis (Interfaces) Tim Quinn (GSE) Jorg Fischer (QA and Parts Lead) SWEA Pre-CDR Peer Review 4

SWEA Electrical Block Diagram SWEA Pre-CDR Peer Review IRAP/CESR UCB 5

SWEA Electrical Requirements – MAVEN-PF-SWEA-002 SWEA Instrument Specification • Functional and Performance Requirements • Resource Allocations (board size, power budget) • Environmental Requirements (thermal, vibration, radiation) – MAVEN-PF-QA-002 UCB Mission Assurance Implementation Plan • Parts Level • Burn-In • Derating – MAVEN-PF-SYS-003 Power Converter Requirements • Power voltages, current, ripple, transients – MAVEN-SWEA-012 FPGA Specification • • • PFDPU CLK/TLM/CMD Interface HV Enable (RAW and MCP) and DAC Control (Sweep and Fixed) Operational Heater Control Pre-amp Input, Test Pulser Output Housekeeping and Memory (external SRAM) I/F SWEA Pre-CDR Peer Review 6

SWEA Digital Board Interfaces • MAVEN-PF-SWEA-001 CESR to SSL ICD – – – – • Preamp Pulse Characteristics Test Pulser Frequencies HV Enable and Converter Synch DAC Control Voltages Sweep Waveforms Analog Housekeeping Connector Pin-out MAVEN-PF-SYS-004 PFDPU ICD – PFDPU Serial I/F description (CMD/CLK/DATA) – Power Interface (28 V/RTN) • MAVEN-PF-SYS-013 Harness – Connector Pin-outs • MAVEN-PF-SYS-003 Power Req. – Power I/F (voltages, current, characteristics) • MAV-RQ-09 -0015 Particle and Fields to Spacecraft ICD – Heater, Thermister and Cover Actuator Interface SWEA Pre-CDR Peer Review 7

Heritage and Design Similarities • MAVEN SWEA digital board has direct heritage from STEREO SWEA: – Minor interface changes (separate connector to SC for temp sensor, heater and actuator, external PFDPU connector) – Changed interface logic to 3. 3 V from 5 V (added translators 54 ACT 244 on FPGA outputs, UT 54 ACS 164245 SEI on pre-amp inputs to FPGA) – Minor FPGA part change (RT 54 SX 72 S from RT 54 SX 32 S) – Removed STE digital circuitry and interface – Removed latch-up circuitry – Minor part changes due to obsolescence, desire to have common parts buy and circuitry • MAVEN SWEA digital board is very similar to MAVEN SWIA and STATIC: – FPGA and SRAM same as SWIA, different than STATIC – Housekeeping (HK MUX and ADC parts) same – Fixed and Sweep DACs same minus offset DACs need for STATIC SWEA Pre-CDR Peer Review 8

Digital Board Design • • • Command/Data Interface to PFDPU Accumulate counts from each of the 16 anodes Bin data for transfer to PFDPU Enable HVPS and MCP high voltage Control voltage sweeps for analyzer inner hemisphere and deflectors Provide programmable threshold for anode pulse amplifiers SRAM for storing lookup tables and accumulators Generate test pulses Control ADC and MUX to read instrument housekeeping monitors Note: Digital board does not control heaters (S/C) or cover actuators (S/C) SWEA Pre-CDR Peer Review 9

FPGA Block Diagram SWEA Pre-CDR Peer Review 10

SWEA and SWIA FPGA Similarities • Commonalities – Both require anode counting frontends – Both implement Command & Telemetry Interfaces (CDI functionality for receiving commands and sending messages) – Housekeeping Control and Message Format – Memory Control – Fixed and Sweep DAC Control – Timing Backbone (reconfigured to accommodate the different accumulation intervals) – Lookup table memory and control (Loader and Checksummer) – High Voltage turn-on is a protected command – Overcurrent Protection (shown in SWEA block diagram) to be implemented identically in both FPGAs • Differences – – – SWIA: 24 Anodes (14 WFOV and 10 NFOV) SWEA: 16 Anodes SWIA: 4 second cycle with 2304 Accumulation Intervals SWEA: 2 second cycle with 488 Accumulation Intervals SWIA Implements Products SWEA Includes Operational Heater Control SWEA Pre-CDR Peer Review 11

Digital Board Status • Board Built and Loaded (MAVEN-PF-SWE-SCH-001 Rev 16) SWEA Digital SWEA Pre-CDR Peer Review 12

Digital Board Status • Board Test complete per MAVEN-PF-SWE-PROC-001 SWEA Pre-CDR Peer Review 13

Digital Board Status • Digital Board Integrated and Tested with EM Analyzer per MAVEN-PFSWE-PROC-002 SWEA Pre-CDR Peer Review 14

Digital Board Status • Fit Check with Mechanical Chassis SWEA Pre-CDR Peer Review 15

PFP Power Distribution SWEA Pre-CDR Peer Review 16

SWEA LVPS Block Diagram – Secondary Voltages • • SWEA Pre-CDR Peer Review +28 VA +/-10% 20 m. A Peak +12 VA +/-5% 8 m. A Peak +5 VA +/-5% 10 m. A Peak -12 VA +/-5% 10 m. A Peak +5 VD +/-5% 40 m. A Peak +3. 3 VD +/-3% 10 m. A Peak +2. 5 VD +/-3% 10 m. A Peak 17

LVPS Status • SWEA LVPS Board built, loaded and in test SWEA Pre-CDR Peer Review 18

SWEA Resources SWEA Power Component Average (m. W) Front-end electronics 776 565 Digital electronics 211 160 Total Secondary 987 725 SWEA LVPS Eff. (75%) 329 242 PFDPU LVPS Eff. (90%) Measured: 196 m. W Peak (m. W) 146 107 1462 1074 Total Allocation Contingency SWEA Pre-CDR Peer Review 1240 15% 19

Electronic Parts • SWEA Active Parts List from MAVEN-PF-QA-003 Common Buy Parts • STATUS: – All parts in house or on order SWEA Pre-CDR Peer Review 20

SWEA and SWIA FPGA Similarities • Immediate Schedule and Tasks – – Integrate and Test Digital Board/EM Analyzer with LVPS PFDPU Interface Test Further sweep Look-up Table (LUT) and memory testing Parts Stress Analysis • Issues – No known issues – Minor changes in layout required for flight • DAC polarity change • Part footprint change SWEA Pre-CDR Peer Review 21