Описание элементов VHDL Дешифратор семисегментного индикатора

Описание элементов VHDL

Дешифратор семисегментного индикатора • • • • • • • library ieee; use ieee. std_logic_1164. all; entity BCD 2 SSD is port ( end BCD 2 SSD; architecture ARCH of BCD 2 SSD is begin process(src) begin end ARCH; end process; src : in std_logic_vector(3 downto 0); display : out std_logic_vector(0 to 6); case src is when when when "0000" "0001" "0010" "0011" "0100" "0101" "0110" "0111" "1000" "1001" others => display <= "1111110"; => display <= "1100000"; => display <= "1011010"; => display <= "1110011"; => display <= "1100101"; => display <= "0110111"; => display <= "0111111"; => display <= "1100010"; => display <= "1111111"; => display <= "1110110"; => display <= "0000000";

D триггер • • • • • • • library ieee; use ieee. std_logic_1164. all; entity DFF is port( CLK, RST, D : in std_logic; Q : out std_logic); end DFF; architecture Example of DFF is signal FF: std_logic; -- Flip Flop main data signal CHG: std_logic; -- Change symbol begin process(CLK, RST, CHG) begin if (RST = '1') THEN FF <= '0'; elsif (CLK'event and CLK = '1') THEN CHG <= '1' after 1 ns; end if; if (CHG = '1') then FF <= D; CHG <= '0' after 1 ns; end if; end process; Q <= FF after 1 ns; end Example;

Счетчик от 0 до F • • • • • • • library ieee; use ieee. std_logic_1164. all; use ieee. STD_LOGIC_UNSIGNED. all; use ieee. std_logic_arith. all; entity count 4 is port ( clk, reset : in std_logic; count: out std_logic_vector(3 downto 0)); end count 4; architecture Example of count 4 is signal count_i: std_logic_vector(3 downto 0); begin process(clk, reset) begin if (reset = '1') then count_i <= "0000"; elsif rising_edge(clk) then count_i <= count_i + '1'; end if; end process; count <= count_i; end Example;

Сдвиговый регистр • • • • • • • • • library IEEE; use entity SHIFT is IEEE. std_logic_1164. ALL; port( end SHIFT; ); a : in std_logic_vector(15 downto 0); sel : in std_logic_vector(2 downto 0); -- Command to shiter -- 000 SHL -- 001 SHR -- 010 ROL -- 011 ROR -- 1 XX pass (no shift) y : out std_logic_vector(15 downto 0) architecture RTL of SHIFT is begin shiftprocess: process(a, sel) begin case sel is WHEN "000" => WHEN "001" => WHEN "010" => WHEN "011" => WHEN OTHERS => end RTL; end process; end case; -- SHL y <= a(14 downto 0) & '0' after 1 ns; -- SHR y <= '0' & a(15 downto 1) after 1 ns; -- ROL y <= a(14 downto 0) & a(15) after 1 ns; -- ROR y <= a(0) & a(15 downto 1) after 1 ns; -- pass it y <= a;