New Product Introduction: 16 Mb Asynchronous SRAM with ECC = Error-Correcting Code High-Speed and Low-Power Asynchronous SRAMs With On-Chip ECC to Improve System Reliability 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering)
Modern Systems Need Reliable SRAMs Modern systems cannot tolerate bit errors in SRAMs Advanced computing systems require reliable high-speed SRAMs as control stores 1 memories Battery-backed systems require reliable low-power SRAMs to store critical data Soft Errors 2 corrupt memory content, resulting in a loss of critical data Error detection and correction is required to ensure data reliability Programmable Logic Controller by Siemens Soft Errors result in malfunction due to corrupted configuration information Router by Cisco Soft Errors result in malfunction due to corrupted configuration information Multi-Function Printer by Canon Soft Errors result in faulty configuration and status information Today’s systems require reliable high-speed and low-power SRAMs with error detection and correction 1 A memory device used to load system configuration registers at boot-up time 2 Data errors caused by background radiation 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 3 a
Cypress Is The SRAM Market Leader Cypress is the world’s largest and most experienced Asynchronous SRAM supplier >40% market share Designed 10 generations of Asynchronous SRAMs Invests more in R&D than any other competitor does Cypress has the broadest Asynchronous SRAM portfolio 600 Asynchronous SRAMs Fast Asynchronous SRAMs from 64 Kb to 32 Mb Mo. BL® (micropower) SRAMs with densities from 64 Kb to 64 Mb Industrial, automotive and rad-hard products Our newest SRAMs with on-chip ECC for single-bit error detection and correction Cypress is the most dependable Asynchronous SRAM supplier Lead times of ≤ 5 weeks, better than 99. 4% on-time delivery Multiple qualified fabs, assembly sites and test sites Legacy part support up to 20 years Cypress is the world’s Asynchronous SRAM leader 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 3 b
Terms You Will Hear Today Asynchronous SRAM An SRAM device in which read or write operations do not require an external clock Fast SRAM High-speed Asynchronous SRAMs with access times ≤ 20 ns Mo. BL® SRAM Low-power Asynchronous SRAMs with less than or equal to 2 -µA/Mb standby current Soft Error A data error caused by background radiation Soft Error Rate (SER) The rate at which a device is predicted to encounter Soft Errors Failure-in-Time (FIT) A reliability measurement of the projected failure rate of a device One FIT equals one projected failure per billion hours Error-Correcting Code (ECC) Encoding and decoding of a bit stream using extra bits to detect and correct bit errors Power. Snooze™ SRAM Fast SRAM with an additional power-saving mode with less than or equal to 2. 5 -µA/Mb deep-sleep current ERR Pin An optional status pin on a Cypress Asynchronous SRAM with ECC that indicates occurrence of single bit errors 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 4
Design Problems Engineers Face FIT rates of <10 FIT/Mb are unavailable in standard SRAMs without error-correction schemes Today's standard SRAMs have FIT rates in the range of 150 -1, 500 FIT/Mb Mitigating Soft Errors with system-level ECC solutions forces undesirable trade-offs System-level Soft Error detection and correction solutions increase design complexity and design cycle time These solutions require additional memory and error-correction chips, increasing board space and cost High-speed, power-sensitive designs require memories with fast access time and low standby current A typical 16 Mb high-speed SRAM with a 10 -ns access time consumes greater than 20 -m. A standby current A typical 16 Mb low-power SRAM with a 16 -µA standby current has an access time greater than 35 ns Cypress 16 Mb Asynchronous SRAM with ECC solves these problems: Assures a FIT rate of <0. 1 FIT/Mb Offers a single-chip solution with on-chip ECC, reducing board space, cost and design complexity Achieves a 10 -ns access time and 12 -µA deep-sleep current (Power. Snooze SRAM) Cypress 16 Mb Asynchronous SRAMs with ECC provide single-chip, reliable memory solutions for both high-speed, low-power applications 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 5
Cypress 16 Mb Asynchronous SRAM vs. Competition’s Fast SRAM Features CY 7 C 1061 xx IS 61/4 WVxx No Offerings Available On-Chip ECC Yes No - Soft Error Rate <0. 1 FIT/Mb >150 FIT/Mb - Voltage Range 1. 65 -5. 5 V 1. 65 -3. 6 V - Access Time (Max. ) 10 ns 8 ns - Operating Current 110 m. A 115 m. A - Data Retention Voltage (Min. ) 1. 0 V 1. 2 V - Deep-Sleep Mode (Power. Snooze) Yes No - Low-Power SRAM Features CY 6216 xx IS 62/65 WVxx R 1 LV 1616 Hx / R 1 LV 1616 Rx 1 On-Chip ECC Yes No Soft Error Rate <0. 1 FIT/Mb >150 FIT/Mb <1 FIT/Mb <6. 25 FIT/Mb Voltage Range 1. 65 -5. 5 V 1. 65 -3. 6 V 2. 7 -3. 6 V Access Time (Max. ) 45 ns 55 ns Standby Current (Max. ) 16 µA 50 µA 8 µA 40 A Data Retention Voltage (Min. ) 1. 0 V 1. 5 V 2. 0 V 1 R 1 LV 1616 Rx is the latest Advanced LPSRAM offering from Renesas 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 7
Asynchronous SRAM Portfolio High Density | Wide Voltage Range | Automotive A, E 1, 2 | On-chip ECC 3 4 Low-Power SRAM (Mo. BL® : More Battery Life) Power. Snooze™ Fast SRAM ECC 3 Non-ECC 3 Quad-SPI, ECC 3 Other Densities NDA Required Contact Sales 32 Mb-128 Mb Non-ECC CY 6218 x 64 Mb; 2. 5, 3. 0 V 55 ns; x 8, x 16 Ind 5 Other Densities NDA Required Contact Sales CY 6216 x 16 Mb; 1. 8 -5. 0 V 45 ns; x 8, x 16, x 32 Ind 5, Auto E 2 CY 7 S 106 x 16 Mb; 1. 8 -5. 0 V 10 ns; x 8, x 16, x 32 Ind 5, Auto E 2 CY 7 C 107 x 32 Mb; 3. 3 V 12 ns; x 8, x 16 Ind 5 CY 6217 x 32 Mb; 2. 5, 3. 0, 5. 0 V 55 ns; x 8, x 16 Ind 5 CY 7 C 106 x 16 Mb; 1. 8, 3. 3 V 10 ns; x 8, x 16, x 32 Ind 5 CY 7 C 106 x 16 Mb; 1. 8 -5. 0 V 10 ns; x 8, x 16, x 32 Ind 5, Auto E 2 CY 6216 x 16 Mb; 1. 8, 3. 0, 5. 0 V 45 ns; x 8, x 16 Ind 5, Auto A 1 2 Mb-16 Mb CY 7 C 105 x 8 Mb; 3. 3 V 10 ns; x 8, x 16 Ind 5 CY 7 C 1012 12 Mb; 3. 3 V 10 ns; x 24 Ind 5 CY 6215 x 8 Mb; 1. 8, 3. 0, 2. 5 -5 V 45 ns; x 8, x 16 Ind 5, Auto A, E 1, 2 CY 7 C 104 x 4 Mb; 3. 3, 5. 0 V 10 ns; x 4, x 8, x 16 Ind 5, Auto A, E 1, 2, RH 6 CY 7 C 1034 6 Mb; 3. 3 V 10 ns; x 24 Ind 5 CY 6214 x 4 Mb; 1. 8, 3. 0, 2. 5 -5 V 45 ns; x 8, x 16 Ind 5, Auto A, E 1, 2 CY 7 C 1010/11 2 Mb; 3. 3 V 10 ns; x 8, x 16 Ind 5, Auto A, E 1, 2 64 Kb-1 Mb Serial SRAM CY 7 C 1024 3 Mb; 3. 3 V 10 ns; x 24 Ind 5 CY 6213 x 2 Mb; 1. 8, 2. 5 -5. 0 V 45 ns; x 8, x 16 Ind 5, Auto A, E 1, 2 CY 7 C 1020 512 Kb; 2. 6, 3. 3, 5. 0 V 10 ns; x 16 Ind 5, Auto E 2 CY 7 C 1019/21/100 x 1 Mb; 2. 6, 3. 3, 5. 0 V 10 ns; x 4, x 8, x 16 Ind 5, Auto A, E 1, 2 CY 6212 x 1 Mb; 2. 5 -5. 0 V 45 ns; x 8, x 16 Ind 5, Auto A, E 1, 2 CY 7 C 185 64 Kb; 5. 0 V 15 ns; x 8 Ind 5 CY 7 C 19 x/1399 256 Kb; 3. 3, 5. 0 V 10 ns; x 4, x 8 Ind 5, Auto A 1 CY 6264 64 Kb; 5. 0 V 55 ns, 70 ns; x 8 Ind 5 1 AEC-Q 100 − 40ºC to +85ºC 4 Fast SRAM with low-power sleep mode 2 AEC-Q 100 − 40ºC to +125ºC 5 Industrial grade − 40ºC to +85ºC 3 Error-correcting code 6 Radiation hardened, military grade − 55ºC to +125ºC CY 62256 256 Kb; 1. 8, 3. 0, 5. 0 V 55 ns; x 8 Ind 5, Auto A, E 1, 2 001 -91190 Rev *F Owner: SAYD Production 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Sampling Development/Concept 10
Fast SRAM Family with ECC Applications Family Table Switches and routers IP phones Test equipment Automotive Computation servers Military and aerospace systems Density Access Time 4 Mb 8 Mb 16 Mb 32 Mb 64 Mb 128 Mb Features MPN CY 7 C 104 x CY 7 C 105 x CY 7 C 106 x CY 7 C 107 x CY 7 C 108 x CY 7 C 109 x 10 ns 12 ns Supply Current (Max. at 85ºC) 45 m. A 60 m. A 110 m. A 150 m. A 200 m. A Block Diagram Access time: 10 ns for 16 Mb (see Family Table) Bus-width configurations: x 8, x 16 and x 32 Wide operating voltage range: 1. 65 -5. 5 V Industrial and automotive temperature grades Industry-standard, Ro. HS-compliant packages Error-Correcting Code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Error indication (ERR) pin to indicate single-bit errors Fast SRAM with ECC SRAM Array ECC Encoder Input Buffer 18 -23 Address Decoder 8, 16, 32 Data ERR I/O Mux Sense Amps SRAM Array ECC Decoder Control Logic CE Collateral WE BHE 1 BLE 2 Availability Preliminary Datasheet: Contact Sales Sampling: Production: 1 Byte high enable 001 -91190 Rev *F OE Owner: SAYD Now (16 Mb) Q 2 2015 (16 Mb) 2 Byte low enable 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 11 a
Mo. BL® SRAM Family With ECC Applications Family Table Programmable logic controllers Handheld devices Multifunction printers Automotive Implantable medical devices Computation servers Density 4 Mb 8 Mb 16 Mb 32 Mb 64 Mb 128 Mb Features Standby Current (Max. at 85ºC) 7 µA 9 µA 16 µA 58 µA 116 µA MPN CY 6214 x CY 6215 x CY 6216 x CY 6217 x CY 6218 x CY 6219 x Standby Current (Typ. at 25ºC) 2. 5 µA 3. 0 µA 4. 7 µA 9. 0 µA 18. 0 µA Block Diagram Access time: 45 ns Standby current: 16 µA for 16 Mb Bus-width configurations: x 8, x 16 and x 32 Wide operating voltage range: 1. 65 -5. 5 V Industrial and automotive temperature grades Industry-standard, Ro. HS-compliant packages Error-Correcting Code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Error indication (ERR) pin to indicate single-bit errors Mo. BL® 3 SRAM with ECC SRAM Array 18 -23 Address Decoder ECC Encoder Input Buffer 8, 16, 32 Data ERR I/O Mux SRAM Array Sense Amps ECC Decoder Control Logic CE Collateral WE BHE 1 BLE 2 Availability Preliminary Datasheet: Contact Sales Sampling: Production: 1 Byte high enable 001 -91190 Rev *F OE Owner: SAYD Now (16 Mb) Q 2 2015 (16 Mb) 2 Byte low enable 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 3 More Battery Life 11 b
Fast SRAM Family with Power. Snooze™ Applications Family Table Programmable logic controllers Handheld devices Multifunction printers Automotive Computation servers Density CY 7 S 104 x CY 7 S 105 x CY 7 S 106 x CY 7 S 107 x CY 7 S 108 x CY 7 S 109 x 10 ns 12 ns Block Diagram Access time: 10 ns for 16 Mb (see Family Table) Power. Snooze: Additional power-saving (deep-sleep) mode Deep-sleep current: 22 µA for 16 Mb (see Family Table) Bus-width configurations: x 8, x 16 and x 32 Wide operating voltage range: 1. 65 -5. 5 V Industrial and automotive temperature grades Industry-standard, Ro. HS-compliant packages Error-Correcting Code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Fast SRAM with Power. Snooze. TM ECC Encoder 20 Address Decoder SRAM Array Power Management Block (Enables Power. Snooze) DS 1 Collateral Input Buffer I/O Mux Sense Amps 8, 16, 32 Data ERR ECC Decoder Control Logic CE OE WE BHE 2 BLE 3 Availability Preliminary Datasheet: Contact Sales Sampling: Production: 1 Deep-sleep 001 -91190 Rev *F Deep Sleep Current (Max. at 85ºC) 10 µA 15 µA 22 µA 92 µA 184 µA Access Time 4 Mb 8 Mb 16 Mb 32 Mb 64 Mb 128 Mb Features MPN Owner: SAYD Now (16 Mb) Q 2 2015 (16 Mb) 2 Byte high enable 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 3 Byte low enable 11 c
Here’s How to Get Started 1. Visit the 16 Mb Asynchronous SRAM with ECC webpage: www. cypress. com/Async. SRAMECC 2. Download the Roadmap for Asynchronous SRAMs: www. cypress. com/Async. Roadmap 3. Request a preliminary datasheet: Contact Sales 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 12
APPENDIX 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 15
16 Mb Mo. BL SRAM Product Selector Guide Part Number Bus Width Access Time # CE Pins ERR Pin Voltage Temp Package CY 62167 G 30 -45 BVXI CY 62167 G 30 -45 ZXI CY 62167 GE 30 -45 BVXI CY 62167 GE 30 -45 ZXI CY 62167 GE-45 ZXI CY 62167 G 18 -55 BVXI CY 62167 GE 18 -55 BVXI CY 62168 GE 30 -45 BVXI CY 62168 G 30 -45 BVXI CY 62162 G 18 -45 BGXI CY 62162 G 30 -45 BGXI x 16 x 16 x 8 x 32 45 ns 45 ns 55 ns 45 ns -40 -85°C -40 -85°C -40 -85°C 48 -VFBGA 48 -TSOP I 48 -VFBGA 119 -PBGA 2 2 2 1 2 2 2 2 No No No Yes Yes No No No 2. 20 -3. 60 V 4. 50 -5. 50 V 1. 65 -2. 20 V 2. 20 -3. 60 V 16 Mb Mo. BL SRAM Part Numbering Decoder CY 6216 X GX XX - XX XX X XI Pb-free Industrial Temperature Grade Chip Enable: Blank = Dual Chip Enable, 1 = Single Chip Enable Package Type: BV = 48 -VFBGA, Z = 48 -TSOP I, BG = 119 -PBGA Speed Grade: 45 = 45 ns, 55 = 55 ns Voltage Range: 30 = 2. 20 -3. 60 V, 18 = 1. 65 -2. 20 V, Blank = 4. 50 -5. 50 V Process Technology: G = 65 nm; X: E = ERR pin, Blank = No ERR pin Bus Width: 7 = x 16, 8 = x 8, 2 = x 32 6216: 16 Mb Mo. BL SRAM Family Company ID: CY = Cypress 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 16 a
16 Mb Fast SRAM Product Selector Guide Part Number Bus Width Temp Package 10 ns 10 ns 10 ns 15 ns 10 ns CY 7 C 1069 G 30 -10 ZSXI x 8 CY 7 C 1069 GE 30 -10 ZSXI x 8 CY 7 C 1061 G 30 -10 ZXI x 16 CY 7 C 1061 GE 30 -10 ZXI x 16 CY 7 C 1061 G 30 -10 ZSXI x 16 CY 7 C 1061 GE 30 -10 ZSXI x 16 CY 7 C 1061 G 30 -10 BVXI x 16 CY 7 C 1061 GE 30 -10 BVXI x 16 CY 7 C 1061 G 30 -10 BV 1 XI x 16 CY 7 C 1061 G 30 -10 BVJXI x 16 CY 7 C 1061 G 18 -15 BV 1 XI x 16 CY 7 C 1062 G 30 -10 BGXI x 32 CY 7 C 1062 GE 30 -10 BGXI x 32 Access Time # CE Pins ERR Pin Voltage -40 -85°C -40 -85°C -40 -85°C -40 -85°C 54 -TSOP II 48 -TSOP I 54 -TSOP II 48 -VFBGA 48 -VFBGA 119 -PBGA 2 2 1 1 2 2 1 2 1 3 3 No Yes No No Yes 2. 20 -3. 60 V 2. 20 -3. 60 V 1. 65 -2. 20 V 2. 20 -3. 60 V 16 Mb Fast SRAM Part Numbering Decoder CY 7 C 106 X GX XX - XX XI Pb-free Industrial Temperature Grade Package Type: Z = 48 -TSOP I, ZS = 54 -TSOP II, BVX = 48 -VFBGA, BG = 119 -PBGA Speed: 10 = 10 ns, 15 = 15 ns Voltage Range: 18 = 1. 65 -2. 20 V, 30 = 2. 20 -3. 60 V, Blank= 4. 50 -5. 50 V Process Technology: G = 65 nm; X: E = ERR pin, Blank = No ERR pin Bus Width: 1 = x 16, 2 = x 32, 9 = x 8 7 C 106: 16 Mb Fast SRAM Family Company ID: CY = Cypress 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 16 b
16 Mb Power. Snooze SRAM Product Selector Guide Part Number Bus Width Access Time # CE Pins ERR Pin Voltage Temp Package CY 7 S 1061 G 30 -10 BVXI CY 7 S 1061 G 30 -10 ZSXI CY 7 S 1061 GE 30 -10 ZXI CY 7 S 1062 G-10 BGXI CY 7 S 1062 G-15 BGXI x 16 x 32 -40 -85°C -40 -85°C 48 -VFBGA 48 -TSOP I 54 -TSOP II 48 -TSOP I 119 -PBGA 10 ns 10 ns 15 ns 1 1 2 1 3 3 No No No Yes No No 2. 20 -3. 60 V 1. 65 -3. 60 V 16 Mb Power. Snooze SRAM Part Numbering Decoder CY 7 S 106 X GX XX - XX XXX I Temperature Grade: Industrial Pb-free Package Type: ZX = 48 -pin TSOP I, ZSX = 54 -pin TSOP II, BVX = 48 -ball VFBGA Speed: 10 = 10 ns, 15 = 15 ns Voltage Range: 18 = 1. 65 -2. 20 V, 30 = 2. 20 -3. 60 V Process Technology: G = 65 nm; X: E = ERR pin, Blank = No ERR pin Bus Width: 1 = x 16, 2 = x 32 7 S 106: 16 Mb Power. Snooze Family (deep-sleep feature) Company ID: CY = Cypress 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 16 c
References and Links Asynchronous SRAM Roadmap: www. cypress. com/Async. Roadmap Cypress Product Selector Guide: www. cypress. com/PSG Knowledge Base Articles: www. cypress. com/Async. KBA Asynchronous SRAM Datasheets: www. cypress. com/Async. Datasheets Application Notes: www. cypress. com/Async. App. Notes Getting Started with Asynchronous SRAM: www. cypress. com/Getting. Started SRAM Board Design Guidelines: www. cypress. com/SRAMDesign. Guidelines Asynchronous SRAM Webpage: www. cypress. com/Async. SRAMECC 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 18
16 Mb SRAM With ECC Solution Value Competitor $15. 34 Competitor Asynchronous Fast SRAM without ECC Price: $15. 341 Additional SRAM for ECC data 2 Price: $3. 233 $3. 23 BOM Integration Value BOM Integration Additional SRAM for ECC data $3. 23 Cost of Programming MCU for ECC logic Board Space Savings Additional Value Cost of Programming MCU for ECC logic Value Added: $0. 154 Board Space Savings Value Added: $0. 015 $0. 01 Total Additional Value Total Value Delivered $0. 16 $18. 73 Async Fast SRAM with ECC: CY 7 C 1061 G 30 -10 BVJXI Total Cost: $16. 67 11% Total Savings: $2. 06 1 Digikey 1 ku price for IS 61 WV 102416 BLL-10 MLI (16 Mb SRAM) 2 4 Mb additional SRAM is used to implement ECC scheme (to store additional 6 parity bits per 32 bits of data) 3 Digikey 1 ku price for IS 61 WV 25616 BLL-10 TL (4 Mb SRAM) 4 5 man-weeks at $3, 000 per man-week = $15, 000 (amortized over 100 ku) 5 0. 15 square-inch space saving at $0. 05 per square inch = $0. 01 001 -91190 Rev *F Owner: SAYD 16 Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) 19
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