Nano-scale CMOS and Low Voltage Analog to Digital

Nano-scale CMOS and Low Voltage Analog to Digital Converter Design Challenges Akira Matsuzawa Tokyo Institute of Technology 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 　1

Contents 1. Introduction 2. Effect of technology scaling on analog performance --- Performance analysis of pipeline ADC --- 3. Design challenges for ADC in nano-scale era --- No use of Operational amplifier -- - Comparator controlled current source - Successive approximation ADC - Sub-ranging ADC 4. Summary 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 2

Performance and applications Pipeline ADC is the major conversion architecture for communications and digital consumer products. Conversion Rate (MHz) 1000 500 300 Graphics HDD/DVD Pipeline ADC Video/ Communication 100 50 30 10 5 DVC/DSC/Printer Servo Automobile 1 General Purpose 0. 5 (µ-Computer) 0. 1 Audio 0. 05 Meter 6 8 10 12 14 16 Resolution (bits) 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 3

Pipeline ADC Folding I/O characteristics makes higher resolution along with pipeline stages. Hold Sample Amplify Transfer characteristics 1 st stage Sample Amp. Sample 1 st Stage 2 nd Stage +Vref Amp. -Vref 2 nd Stage Sample +Vref 0 Amp. Sample Amp. Ｘ２ 2006. 10. 25. +Vref -Vref 0 1 -Vref A. Matsuzawa, Tokyo Tech. +Vref Ｘ２ 1 0 1 -Vref 4

Speed and power Conversion speed has saturated at 200 MHz Smaller m. W/MHz is needed for low power operation. 0. 3 m. W/MHz for 10 bit and 1 m. W/MHz for 12 bit are the bottom lines. 12 b 10 b 1995 -2006 200 MHz 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 5

Effect of technology scaling on analog performance Technology scaling and performance of pipeline ADC 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 　6

Operating voltage trend Operating voltage of scaled device will keep about 1 V Design Rule Analog High Analog Low Digital High Design rule　(nm) Operating voltage　(V) ITRS 2003 ITRS 2001 About 1 V operation Digital Low (Low leak) 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 7

Operational amplifier for ADC Pipeline ADC needs high performance amplifier. The output signal range will be reduced along with voltage lowering. Vdd 2 Veff Vin+ Vin- vout+ Gain Boost amp. vout- Output signal range Vs=Vdd-0. 7 V Vs=0. 5 V @Vdd=1. 2 V Vs=0. 3 V @Vdd=1. 0 V Vs=Vdd-4 Veff 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 8

Requirements for operational amplifier Higher resolution requires higher open loop gain. Higher conversion frequency requires higher closed loop GBW. Sampling DC gain N: ADC resolution M：Stage resolution Amplify for 1. 5 b pipeline ADC Closed loop gain-bandwidth 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 9

k. T/C noise Larger SNR requires larger capacitance and larger signal swing. Low signal swing increases required capacitance. φ n: configuration coefficient vn v out CL VFS=5 V VFS=3 V n=2 14 bit VFS=2 V R SNR (d. B) CL VFS=1 V 12 bit 10 bit 0. 1 1 10 100 Capacitance (p. F) 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 10

Effect of technology scaling Gain bandwidth of Op. Amp increases along with technology scaling. However, can we increase every needed performances for ADCs? GBW: 10 GHz 90 nm Conversion freq. : 1 GHz 0. 25 um GBW: 2 GHz Conversion freq. : 200 MHz　 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 11

Technology scaling for analog Technology scaling can reduce parasitic capacitances. However signal capacitance will increase to keep the same SNR at lower voltage operation. Parasitic capacitance smaller Operating voltage lower Signal swing lower Signal capacitance larger Voltage gain lower Technology scaling Signal Cap. Parasitic Cap. 2006. 10. 25. A. Matsuzawa, Tokyo Tech. Parasitic Cap. 12

Performance model for pipeline ADC We have developed the performance model for pipeline ADC that can treat technology scaling. Op. Amp 2006. 10. 25. A. Matsuzawa, “Analog IC Technologies for Future Wireless Systems, ” IEICE, Tan on Electronics, Vol. E 89 C, No. 4, pp. 446 -454, April, 2006. A. Matsuzawa, Tokyo Tech. 13

Scaling and analog device and circuit parameters Gate width and capacitances decrease with technology scaling. (a)WN, WP[μm/m. A], VA_N, VA_P[V] Veff=0. 175 V DR Cap. [f. F/m. A], f. T[GHz] W[μm/m. A] Cgs W Cgd (b)Cpi_N, Cpi_P, Cpo[f. F/m. A], ωp 2_N, ωp 2_P[GHz] DR f. T S: Scaling factor L[μm] 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 14

Determination of signal capacitance Larger resolution requires larger signal capacitance. Furthermore, Voltage lowering increases signal capacitance more. Vdd 2 Ve ff Vin- + vout- 14 bit 12 bit Co[p. F] Vin+ Gain Boost amp. vout Output signal range Vdd-4 Veff 10 bit 2 Veff 8 bit 90 nm 0. 13μm 0. 18μm 0. 25μm 0. 35μm Vdd 1. 2 V 1. 5 V 1. 8 V 2. 5 V 3. 3 V Vsig_pp 1. 0 V 1. 6 V 2. 2 V 3. 6 V 5. 2 V 2006. 10. 25. 0. 05 A. Matsuzawa, Tokyo Tech. 0. 1 0. 5 DR[μm] 15

Performance curve Performance exhibits convex curve. There is the peak conversion frequency and the optimum current. Current increase results in increase of parasitic capacitances and decrease of conversion frequency in the higher current region. ② ③ ① ①Co≫Cpo, Cpi ②Cpi

8 bit 0. 13 um attains highest conversion frequency in a low current region. However 90 nm is over striding 0. 13 um along with increase of the current. 0. 13μm 2006. 10. 25. 90 nm A. Matsuzawa, Tokyo Tech. 17

10 bit The best design rule depends on operating current. 0. 35 um attains highest conversion frequency in low operating current region! 0. 35μm 2006. 10. 25. 0. 25μm 0. 18μm 0. 13μm A. Matsuzawa, Tokyo Tech. 90 nm 18

12 bit Relaxed design rule is suitable for wider current range. 0. 35μm 2006. 10. 25. 0. 25μm A. Matsuzawa, Tokyo Tech. 0. 18μm 19

14 bit Scaled CMOS is not suitable for higher resolution ADC. 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 20

Performance summary Scaled CMOS is effective for just low resolution ADC. Scaled CMOS is not effective for high resolution ADC. ８ bit 12 bit 2006. 10. 25. 10 bit 14 bit A. Matsuzawa, Tokyo Tech. 21

Voltage gain VA decreases with scaling and operating voltage lowering. High gain can not be expected. NMOS LV operation 2006. 10. 25. PMOS LV operation A. Matsuzawa, Tokyo Tech. 22

Voltage gain of operational amplifier Voltage gain of Op. Amp for scaled CMOS and LV operation is 80 d. B at most. Less than 10 bit ADC can be designed with scaled and low voltage CMOS. Total gain is 80 d. B @max Vin+ Vin- vout+ Gain Boost amp. 40 d. B vout 20 d. B 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 23

Design challenges for ADC in nano-scale era --- No use of Operational amplifier -- - Comparator controlled current source - Successive approximation ADC - Sub-ranging ADC 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 　24

Design rule and Speed in Comparator Gain bandwidth (=Speed) is inversely proportional to the L 2 (channel length). Technology scaling is still effective to increase the comparator speed and to reduce operating current. Furthermore, low voltage operation, such as 0. 5 V, is available. R R Isink 2006. 10. 25. R R Isink A. Matsuzawa, Tokyo Tech. 25

Comparator controlled current source can realize the virtual ground. Now challenge for not use of Op. Amp in ADC design has started. Conventional Op. Amp T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H. Lee, “Comparator. Based Switched-Capacitor Circuits For Scaled CMOS Technologies, ” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574 -575. Feb. 2006. Comparator controlled current source Vx is reaching the virtual ground voltage asymptotically Vx is reaching the virtual ground voltage with constant rate 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 26

Realistic comparator controlled current source Time delay (Vx Vo) causes voltage offset. Small inverse current source has been introduced. The offset voltage can be reduced and does not effect the conversion linearity. I 2<< I 1 T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H. Lee, “Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies, ” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574 -575. Feb. 2006. 10. 25. 10 b, 8 MHz ADC has been developed. Pd=2. 5 m. W. Lowest Pd/MHz A. Matsuzawa, Tokyo Tech. 27

Successive approximation ADC has been used long time as a low power and low speed ADC. It doesn’t require Op. Amp but capacitor array and comparator. Thus this architecture looks suitable for scaled and low voltage CMOS. Now challenge for renewal of this conventional architecture has started. Successive approximation ADC Eight interleaved SA-ADCs with 90 nm CMOS attain 600 MHz operation. SA-ADC D. Draxelmayr, “A 6 b 600 MHz 10 m. W ADC Array in Digital 90 nm CMOS, ” IEEE, ISSCC 2004, Dig. of Tech. Papers, pp. 264 -265, Feb. 2004. 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 28

Improvement of SA-ADC Asynchronous clock increases conversion frequency. Use of proper radix reduces capacitance. Asynchronous clock Capacitor ladder with some radix number 6 bit 600 MHz 5. 3 m. W ADC has been realized with 0. 13 um CMOS S. W. M. Chen and R. W. Brodersen, “A 6 b 600 MS/s 5. 3 m. W Asynchronous ADC in 0. 13 um CMOS, ” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574 -575. Feb. 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 29

Sub-ranging ADC also doesn't require Op. Amp and suitable for LV operation. However it requires low offset voltage comparators. Use of positive feedback technique has realized low offset voltage. Technology revival has been found. Pd/MHz =0. 75 m. W/MHz which is lowest value!! Positive Feedback CKT 7]Y. Shimizu, S. Murayama, K. Kudoh, H. Yatsuda, A. Ogawa, “ A 30 mw 12 b 40 MS/s Subranging ADC with a High-Gain Offset-Canceling Positive-Feedback Amplifier in 90 nm Digital CMOS, ” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 222 -225. Feb. 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 30

Summary • Technology scaling is effective for increasing analog performance if not so much higher SNR is required. • Technology scaling is not effective for increasing analog performance if higher SNR is required, and sometimes degrades it. • Increase of signal capacitance to keep the SNR high at low voltage operation is essential serious issue for use of scaled CMOS. • Furthermore, Gain lowering of Op. Amp due to technology scaling and voltage lowering becomes serious issues. • Design challenges for ADC has been started. • No use of Op. Amp is a common idea. • Technology revivals have been found and the performance has been improved. Further improvement will be expected in future. 2006. 10. 25. A. Matsuzawa, Tokyo Tech. 31