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Microprocessor Systems and Instrumentation SOE 2121 1 Microprocessor Systems and Instrumentation SOE 2121 1

Microprocessor Systems and Instrumentation SOE 2121 Number Systems 2 Microprocessor Systems and Instrumentation SOE 2121 Number Systems 2

Machine code: 01010011010100100101001001000011 1100010100100101000100101001010000101010010111000100 1010100100010010101001001010001 0010101001001010000101010010111 00010111000100101010010001001010100 1001010001001010100100101000010 1010010111000100101010010001 001010100100101000100100101001100100101000100010011 0010010100010101001001010000 101010010111000100101010010010100010101000 111110010010100101000100010010111 3 Machine code: 01010011010100100101001001000011 1100010100100101000100101001010000101010010111000100 1010100100010010101001001010001 0010101001001010000101010010111 00010111000100101010010001001010100 1001010001001010100100101000010 1010010111000100101010010001 001010100100101000100100101001100100101000100010011 0010010100010101001001010000 101010010111000100101010010010100010101000 111110010010100101000100010010111 3

Machine code: 01010001 00001111 0101 01110001 10010101 00101001010 0100 1010 10010001 00100101 10001010 110001010010 Machine code: 01010001 00001111 0101 01110001 10010101 00101001010 0100 1010 10010001 00100101 10001010 110001010010 00010100 00100100 01110001 00100101 01000010 10001010 01001010 10010111 00101001 00010001 10010010 11000100 10100100 11001001 10100101010 0001 1010 0100 00101010 00010111 01010010 00110010100 10101001010 00101001 00101000 01011100 101001010 00010010 01010001 0010101001001001 0010 10101001 00010010 10101001 01011100 01001001 01010000 10100010011 00010010 101001010 4

Machine code: DB 03 82 83 F 2 64 82 E 2 33 74 Machine code: DB 03 82 83 F 2 64 82 E 2 33 74 99 82 83 EE 99 AB 37 64 55 99 82 E 7 55 72 56 EE 64 55 99 F 2 99 97 5 E 4 B E 7 F 2 EE E 7 64 EE 55 64 83 82 55 64 43. . . 67 83 F 2 E 7 EE 99 EE 85 82 83 F 2 E 7 55 E 7 44 99 82 83 F 2 99 F 2 34 55 99 82 83 55 83 77 64 55 99 82 64 82 62 EE 64 55 99 EE 99 A 3 E 7 EE 64 55 E 7 55 D 9 F 2 E 7 EE 99 F 2 76 FF 83 F 2 E 7 55 83 F 5 5

The Decimal System Decimal Number 38 O 7: 3 x 1 OOO ( = The Decimal System Decimal Number 38 O 7: 3 x 1 OOO ( = 1 O 3) 3 OOO 8 x 1 OO ( = 1 O 2) 8 OO O x 1 O ( = 1 O 1) OO 7 x 1 ( = 1 OO) 7 ---38 O 7 Total: 6

The Binary System Binary Number 1 O 11: 1 x 8 ( = 2 The Binary System Binary Number 1 O 11: 1 x 8 ( = 2 3) 8 O x 4 ( = 2 2) O 1 x 2 ( = 2 1) 2 1 x 1 ( = 2 O) 1 Total: -11 7

The Binary System Bit value: 128 64 32 16 Power of 2: 27 26 The Binary System Bit value: 128 64 32 16 Power of 2: 27 26 25 24 Number: 1 0 0 1 8 4 2 1 23 22 21 2 O 0 1 1 0 8

The Decimal and Binary Systems Decimal Number 3 x 1 OOO 8 x 1 The Decimal and Binary Systems Decimal Number 3 x 1 OOO 8 x 1 OO O x 1 O 7 x 1 38 O 7: ( = 1 O 3) ( = 1 O 2) ( = 1 O 1) ( = 1 OO) Total: Binary 1 O 1 1 Number 1 O 11: x 8 ( = 2 3) x 4 ( = 2 2) x 2 ( = 2 1) x 1 ( = 2 O) Total: 3 OOO 8 OO OO 7 ---38 O 7 8 O 2 1 -11 9

The Hexadecimal System Hexadecimal Number 21 AF: (Base 16) 2 x 4 O 96 The Hexadecimal System Hexadecimal Number 21 AF: (Base 16) 2 x 4 O 96 ( = 163) 8192 1 x 256 ( = 162) 256 A x 16 ( = 161) 16 O F x 1 ( = 16 O) 15 ---8623 Total: 10

Number Systems Decimal Numbers (Base 1 O) 1 O symbols: O 1 2 3 Number Systems Decimal Numbers (Base 1 O) 1 O symbols: O 1 2 3 4 5 6 7 8 9 Binary Numbers (Base 2) 2 symbols: O 1 Hexadecimal Numbers(Base 16) 16 symbols: O 1 2 3 4 5 6 7 8 9 A B C D E F 11

Brain Exercises (Neurobics) * Binary counting on fingers (and toes after ? ) * Brain Exercises (Neurobics) * Binary counting on fingers (and toes after ? ) * Binary Arithmetic + Addition - Subtraction / Division * Multiplication * Hexadecimal Arithmetic + Addition - Subtraction / Division * Multiplication 12

HEX BINARY O 1 2 3 4 5 6 7 8 9 A B HEX BINARY O 1 2 3 4 5 6 7 8 9 A B C D E F OOOO 1 O OO 11 O 1 OO O 1 O 1 O 11 O O 111 1 OOO 1 1 O 1 O 1 O 11 11 OO 11 O 1 111 O 1111 DECIMAL O 1 2 3 4 5 6 7 8 9 1 O 11 12 13 14 15 13

Converting between Binary and Hexadecimal Binary: Hex: 0010 1100 2 C 32+8+4=44 32+12=44 14 Converting between Binary and Hexadecimal Binary: Hex: 0010 1100 2 C 32+8+4=44 32+12=44 14

Converting between Binary and Hexadecimal 111 O 1 OO 111 O 1 12 AB Converting between Binary and Hexadecimal 111 O 1 OO 111 O 1 12 AB = 111 O 1 OO 1 11 O 1 E 9 D = 1 2 A B OOO 1 O 1 O 11 15

Number conversions - Hex to Decimal: Convert 1234 hex to decimal: 163 162 161 Number conversions - Hex to Decimal: Convert 1234 hex to decimal: 163 162 161 4096 256 16 1 2 160 1 3 4 1 2 3 4 x 4096 = 4096 x 256 = 512 x 16 = 48 x 1 = 4 + ----16

Number conversions - Decimal to Binary: Convert 1234 decimal to binary: 210 29 28 Number conversions - Decimal to Binary: Convert 1234 decimal to binary: 210 29 28 27 26 25 24 23 22 21 20 1024 512 256 128 64 32 16 8 4 2 1 - 1 0 0 1234 - 1024 = 210 - 128 82 - 64 = 82 = 18 18 - 16 = 2 2 - 2 = 0 So 1234 decimal = 100 1101 0010 binary 17

Number conversions - Binary to Hex: eg binary number 110100111010 First divide up FROM Number conversions - Binary to Hex: eg binary number 110100111010 First divide up FROM THE RIGHT into groups of 4 bits: 1 1010 0111 0101 1010 Then use the hex table (or better your brain) to write the hex values: 1 1 1010 A 0111 7 0101 5 1010 A Note: learn 0 -9 and remember A=1010 and C=1100 18

HEX BINARY O 1 2 3 4 5 6 7 8 9 A B HEX BINARY O 1 2 3 4 5 6 7 8 9 A B C D E F OOOO 1 O OO 11 O 1 OO O 1 O 1 O 11 O O 111 1 OOO 1 1 O 1 O 1 O 11 11 OO 11 O 1 111 O 1111 DECIMAL O 1 2 3 4 5 6 7 8 9 1 O 11 12 13 14 15 19

Negative Numbers - Twos Complement form: To form a negative number, for example -3, Negative Numbers - Twos Complement form: To form a negative number, for example -3, first invert (ones complement) the positive number of the same magnitude (+3), then add one: 00000011 11111100 00000001+ -------11111101 +3 invert to give ones complement add one result is -3 (Hex FD) 20

Negative Numbers: Most negative number -128 Most positive number +127 7 0 1 0 Negative Numbers: Most negative number -128 Most positive number +127 7 0 1 0 0 0 0 7 0 0 1 1 1 1 Note: bit 7 carries the sign information 1=negative 0=positive 21

Negative Numbers: 0111 1111 0111 1110 | 0000 0011 0000 0010 0001 0000 1111 Negative Numbers: 0111 1111 0111 1110 | 0000 0011 0000 0010 0001 0000 1111 1110 1111 1101 | 1000 0001 1000 0000 7 F 7 E +127 +126 03 02 01 00 FF FE FD +3 +2 +1 0 -1 -2 -3 81 80 -127 -128 22

Signed and Unsigned Arithmetic: Why does it work for both unsigned numbers (0 to Signed and Unsigned Arithmetic: Why does it work for both unsigned numbers (0 to 255) and signed numbers (-128 to +127)? Unsigned Data 253 1 --254 FD 01+ --FE Signed -3 +1 ---2 23

Binary Coded Decimal: Each decimal digit is encoded as a 4 bit binary number: Binary Coded Decimal: Each decimal digit is encoded as a 4 bit binary number: O 1 2 3 4 5 6 7 8 9 OOOO 1 O OO 11 O 1 OO O 1 O 1 O 11 O O 111 1 OOO 1 eg decimal 42 0100 0010 4 2 What is this value in Hexadecimal? (Note 42 in binary is 0010 1010 Hex 2 A) 24

Binary Coded Decimal: Range of BCD numbers in one byte 00 - 99 Reading Binary Coded Decimal: Range of BCD numbers in one byte 00 - 99 Reading a BCD number in hex gives the decimal value 25

HEX BINARY O 1 2 3 4 5 6 7 8 9 A B HEX BINARY O 1 2 3 4 5 6 7 8 9 A B C D E F OOOO 1 O OO 11 O 1 OO O 1 O 1 O 11 O O 111 1 OOO 1 1 O 1 O 1 O 11 11 OO 11 O 1 111 O 1111 DECIMAL O 1 2 3 4 5 6 7 8 9 1 O 11 12 13 14 15 26

ASCII Table: MSD->0 LSD 0 NUL 1 SOH 2 STX 3 ETX 4 EOT ASCII Table: MSD->0 LSD 0 NUL 1 SOH 2 STX 3 ETX 4 EOT 5 ENQ 6 ACK 7 BEL 8 BS 9 HT A LF B VT C FF D CR E SO F SI 1 2 3 4 5 6 7 DLE DC 1 DC 2 DC 3 DC 4 NAK SYN ETB CAN EM SUB ESC FS GS RS VS SP ! " # $ % & ' ( ) * + , . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ ` ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ DEL 27

The Byte 7 6 5 4 3 2 1 0 1 Byte = 8 The Byte 7 6 5 4 3 2 1 0 1 Byte = 8 bits Contains one of 256 possible patterns OOOOOOO 1 OOOOOO 1 O OOOOOO 11 OOOOO 1 OO | 1111 Range $OO-$FF = O to 255 28

The Byte 7 Most Significant Bit 6 5 4 3 2 1 0 Least The Byte 7 Most Significant Bit 6 5 4 3 2 1 0 Least Significant Bit 29

Which is Most Significant? A typical lecturer’s salary might be: £ 93, 878 Most Which is Most Significant? A typical lecturer’s salary might be: £ 93, 878 Most Significant Digit Least Significant Digit 30

Hexadecimal Representation: Binary Hex Meaning 0100 1111 1010 41 41 41 FF FF A Hexadecimal Representation: Binary Hex Meaning 0100 1111 1010 41 41 41 FF FF A 5 Unsigned Binary ASCII code BCD number Signed Binary Unsigned Binary Opcode 0001 1111 0101 7 6 5 4 Value 3 2 1 65 Decimal A 41 Decimal -1 Decimal 255 Decimal LDA 0 31

Brain Exercises (Neurobics) * Binary counting on fingers (and toes after ? ) * Brain Exercises (Neurobics) * Binary counting on fingers (and toes after ? ) * Binary Arithmetic + Addition - Subtraction / Division * Multiplication * Hexadecimal Arithmetic + Addition - Subtraction / Division * Multiplication 32

Introduction Load and Store Transfer 33 Introduction Load and Store Transfer 33

Not Recommended Book: 65 O 2 Assembly Language Programming by L A Leventhal Pub: Not Recommended Book: 65 O 2 Assembly Language Programming by L A Leventhal Pub: Osborne/Mc. Graw-Hill 34

Assembly Language Advantages: Fastest possible program (on a particular processor) Smallest size program (cheaper Assembly Language Advantages: Fastest possible program (on a particular processor) Smallest size program (cheaper ROM) Smallest RAM requirement (cheaper RAM) Disadvantages: Much longer software development time Programs more difficult to debug Programs not portable 35

Assembly Language: When is it used? MASS PRODUCTION Where the lowest possible production cost Assembly Language: When is it used? MASS PRODUCTION Where the lowest possible production cost is required and longer more expensive software development time is acceptable. eg microwave oven, mobile phone HIGH SPEED APPLICATIONS Where a high level language would not respond quickly enough. eg high speed data acquisition system Notes: faster processors, critical bits in assembler, smallest physical size eg Pacemaker where power consumption is also a consideration. 36

Microprocessor Systems and Instrumentation SOE 2121 Number Systems 37 Microprocessor Systems and Instrumentation SOE 2121 Number Systems 37

Machine code: 01010011010100100101001001000011 1100010100100101000100101001010000101010010111000100 1010100100010010101001001010001 0010101001001010000101010010111 00010111000100101010010001001010100 1001010001001010100100101000010 1010010111000100101010010001 001010100100101000100100101001100100101000100010011 0010010100010101001001010000 101010010111000100101010010010100010101000 111110010010100101000100010010111 38 Machine code: 01010011010100100101001001000011 1100010100100101000100101001010000101010010111000100 1010100100010010101001001010001 0010101001001010000101010010111 00010111000100101010010001001010100 1001010001001010100100101000010 1010010111000100101010010001 001010100100101000100100101001100100101000100010011 0010010100010101001001010000 101010010111000100101010010010100010101000 111110010010100101000100010010111 38

Machine code: 01010001 00001111 0101 01110001 10010101 00101001010 0100 1010 10010001 00100101 10001010 110001010010 Machine code: 01010001 00001111 0101 01110001 10010101 00101001010 0100 1010 10010001 00100101 10001010 110001010010 00010100 00100100 01110001 00100101 01000010 10001010 01001010 10010111 00101001 00010001 10010010 11000100 10100100 11001001 10100101010 0001 1010 0100 00101010 00010111 01010010 00110010100 10101001010 00101001 00101000 01011100 101001010 00010010 01010001 0010101001001001 0010 10101001 00010010 10101001 01011100 01001001 01010000 10100010011 00010010 101001010 39

Machine code: DB 03 82 83 F 2 64 82 E 2 33 74 Machine code: DB 03 82 83 F 2 64 82 E 2 33 74 99 82 83 EE 99 AB 37 64 55 99 82 E 7 55 72 56 EE 64 55 99 F 2 99 97 5 E 4 B E 7 F 2 EE E 7 64 EE 55 64 83 82 55 64 43. . . 67 83 F 2 E 7 EE 99 EE 85 82 83 F 2 E 7 55 E 7 44 99 82 83 F 2 99 F 2 34 55 99 82 83 55 83 77 64 55 99 82 64 82 62 EE 64 55 99 EE 99 A 3 E 7 EE 64 55 E 7 55 D 9 F 2 E 7 EE 99 F 2 76 FF 83 F 2 E 7 55 83 F 5 40

HEX BINARY O 1 2 3 4 5 6 7 8 9 A B HEX BINARY O 1 2 3 4 5 6 7 8 9 A B C D E F OOOO 1 O OO 11 O 1 OO O 1 O 1 O 11 O O 111 1 OOO 1 1 O 1 O 1 O 11 11 OO 11 O 1 111 O 1111 DECIMAL O 1 2 3 4 5 6 7 8 9 1 O 11 12 13 14 15 41

The Byte 7 6 5 4 3 2 1 0 1 Byte = 8 The Byte 7 6 5 4 3 2 1 0 1 Byte = 8 bits Contains one of 256 possible patterns OOOOOOO 1 OOOOOO 1 O OOOOOO 11 OOOOO 1 OO | 1111 Range $OO-$FF = O to 255 42

The Byte 7 Most Significant Bit 6 5 4 3 2 1 0 Least The Byte 7 Most Significant Bit 6 5 4 3 2 1 0 Least Significant Bit 43

Which is Most Significant? A typical lecturer’s salary might be: £ 93, 878 Most Which is Most Significant? A typical lecturer’s salary might be: £ 93, 878 Most Significant Digit Least Significant Digit 44

The Byte 7 6 5 4 3 2 1 0 1 Byte = 8 The Byte 7 6 5 4 3 2 1 0 1 Byte = 8 bits Contains one of 256 possible patterns OOOOOOO 1 OOOOOO 1 O OOOOOO 11 OOOOO 1 OO | 1111 Range $OO-$FF = O to 255 45

Hexadecimal Representation: Binary Hex Meaning 0100 1111 1010 41 41 41 FF FF A Hexadecimal Representation: Binary Hex Meaning 0100 1111 1010 41 41 41 FF FF A 5 Unsigned Binary ASCII code BCD number Signed Binary Unsigned Binary Opcode 0001 1111 0101 7 6 5 4 Value 3 2 1 65 Decimal A 41 Decimal -1 Decimal 255 Decimal LDA 0 46

6502 Programmer’s Model 7 Microprocessor 7 Memory 0 FFFF 0 A X 8 Y 6502 Programmer’s Model 7 Microprocessor 7 Memory 0 FFFF 0 A X 8 Y PC 00000001 SP 15 NV-BDIZC PS STACK PAGE ZERO 0200 01 FF 0100 00 FF 0000 47

Memory 65536 bytes numbered in decimal: in hex: in binary: O - 65535 OOOO Memory 65536 bytes numbered in decimal: in hex: in binary: O - 65535 OOOO - FFFF OOOO - 1111 The number of each memory location is known as its ADDRESS 2 Bytes are required to hold an address which is 16 bits 48

Instruction Formats One byte instructions: OPCODE Two byte instructions: OPCODE OPERAND Three byte instructions: Instruction Formats One byte instructions: OPCODE Two byte instructions: OPCODE OPERAND Three byte instructions: OPCODE OPER AND 49

Load and Store Instructions 50 Load and Store Instructions 50

The LDA Instruction Copy the contents of memory location 8 O into the A The LDA Instruction Copy the contents of memory location 8 O into the A register: LDA 8 O This instruction uses zero page addressing since address $8 O is on page zero 51

The LDA Instruction and the Instruction Set Sheet Assembly Language: Machine Code: LDA 8 The LDA Instruction and the Instruction Set Sheet Assembly Language: Machine Code: LDA 8 O A 5 8 O Instruction Set Sheet Entry: A 5 3 Opcode: A 5 Time: 3 clock cycles Length: 2 bytes 52

The LDA Instruction and the Instruction Set Sheet +-----------------------+ | |Immed| ABS | ZP The LDA Instruction and the Instruction Set Sheet +-----------------------+ | |Immed| ABS | ZP |Effect on | | Operation |len=2|len=3|len=2|the flags: | | |OP n|OP n| NV-BDIZC | +-----------+-----+----------+ | LDA | A : = M |A 9 2|AD 4|A 5 3| N. . . Z. | Assembly Language: Machine Code: LDA 8 O A 5 8 O Instruction Set Sheet Entry: A 5 3 Opcode: Time: Length: A 5 3 clock cycles 2 bytes 53

The LDA Instruction and the Instruction Set Sheet Assembly Language: LDA 8 O Machine The LDA Instruction and the Instruction Set Sheet Assembly Language: LDA 8 O Machine Code: A 5 8 O Instruction Set Sheet Entry: A 5 3 Opcode: A 5 Time: 3 clock cycles Length: 2 bytes Effect on the Flags: N. . . Z. N and Z changed depending on the value that is loaded The N flag becomes the sign bit (7) of the value loaded The Z flag is 1 if the value loaded is zero The Z flag is O if the value loaded is not zero 54

Load and Store instructions Absolute Zero Page LDA 1234 LDA 8 O STA 1234 Load and Store instructions Absolute Zero Page LDA 1234 LDA 8 O STA 1234 STA 8 O LDX 1234 LDX 8 O STX 1234 STX 8 O LDY 1234 LDY 8 O STY 1234 STY 8 O 55

Immediate Addressing Instruction Machine code: LDA #AA A 9 AA LDX #FF A 2 Immediate Addressing Instruction Machine code: LDA #AA A 9 AA LDX #FF A 2 FF LDY #O 1 AO O 1 56

Don’t mix these up! Zero Page: LDA OO Immediate: LDA #OO 57 Don’t mix these up! Zero Page: LDA OO Immediate: LDA #OO 57

Transfer Instructions 58 Transfer Instructions 58

Transfer instructions: TAX Copy register A to register X The old value in X Transfer instructions: TAX Copy register A to register X The old value in X is lost Register A is not affected 59

Transfer instructions: TAX TAY TXA TYA (TXS TSX) All 1 byte Long Implied Addressing Transfer instructions: TAX TAY TXA TYA (TXS TSX) All 1 byte Long Implied Addressing 2 Clock Cycles Flags as for LDA 60

Arithmetic Instructions ADC SBC 61 Arithmetic Instructions ADC SBC 61

Negative Numbers 62 Negative Numbers 62

Negative Numbers - Twos Complement form: To form a negative number, for example -3, Negative Numbers - Twos Complement form: To form a negative number, for example -3, first invert (ones complement) the positive number of the same magnitude (+3), then add one: 00000011 11111100 00000001+ -------11111101 +3 invert to give ones complement add one result is -3 (Hex FD) 63

Negative Numbers: Most negative number -128 Most positive number +127 7 0 1 0 Negative Numbers: Most negative number -128 Most positive number +127 7 0 1 0 0 0 0 7 0 0 1 1 1 1 Note: bit 7 carries the sign information 1=negative 0=positive 64

Signed and Unsigned Arithmetic: Why does it work for both unsigned numbers (0 to Signed and Unsigned Arithmetic: Why does it work for both unsigned numbers (0 to 255) and signed numbers (-128 to +127)? Unsigned Data 253 1 --254 FD 01+ --FE Signed -3 +1 ---2 65

ADC 66 ADC 66

Addition: CLC LDA 8 O ADC 81 STA 82 67 Addition: CLC LDA 8 O ADC 81 STA 82 67

Two byte arithmetic: How do we do it in decimal? 36 25 + --61 Two byte arithmetic: How do we do it in decimal? 36 25 + --61 68

Addition and Subtraction: CLC SEC LDA 8 O ADC 81 SBC 81 STA 82 Addition and Subtraction: CLC SEC LDA 8 O ADC 81 SBC 81 STA 82 69

Two byte arithmetic: First Number: Second Number: Result: LSB MSB 80 82 84 81 Two byte arithmetic: First Number: Second Number: Result: LSB MSB 80 82 84 81 Addition: 83 85 Subtraction: CLC LDA ADC STA 8 O 82 84 81 83 85 LSBs MSBs SEC LDA SBC STA 8 O 82 84 81 83 85 LSBs MSBs 70

Decimal Arithmetic 71 Decimal Arithmetic 71

6502 Programmer’s Model 7 Microprocessor 7 Memory 0 FFFF 0 A X 8 Y 6502 Programmer’s Model 7 Microprocessor 7 Memory 0 FFFF 0 A X 8 Y PC 00000001 SP 15 NV-BDIZC PS STACK PAGE ZERO 0200 01 FF 0100 00 FF 0000 72

Decimal Arithmetic (BCD): Addition: Subtraction: SED CLC LDA 8 O ADC 81 STA 82 Decimal Arithmetic (BCD): Addition: Subtraction: SED CLC LDA 8 O ADC 81 STA 82 CLD SEC LDA 8 O SBC 81 STA 82 CLD 73

Logical Instructions 74 Logical Instructions 74

Logical Operations: 75 Logical Operations: 75

Logical Operations: And: AND 76 Logical Operations: And: AND 76

Logical Operations: And: AND Or: ORA 77 Logical Operations: And: AND Or: ORA 77

Logical Operations: And: AND Or: ORA Exclusive Or: EOR 78 Logical Operations: And: AND Or: ORA Exclusive Or: EOR 78

AND 79 AND 79

The AND Instruction: LDA #A 9 AND #OF Result: 1 O 1 O 1 The AND Instruction: LDA #A 9 AND #OF Result: 1 O 1 O 1 OO 1 OOOO 1111 ----OOOO 1 (A) (M) Any O in the mask will clear the corresponding bit in A to O Any 1 in the mask will leave the corresponding bit in A unchanged 80

OR 81 OR 81

The ORA Instruction: LDA #A 9 ORA #OF Result: 1 O 1 O 1 The ORA Instruction: LDA #A 9 ORA #OF Result: 1 O 1 O 1 OO 1 OOOO 1111 ----1010 1111 (A) (M) Any 1 in the mask will set the corresponding bit in A to 1 Any 0 in the mask will leave the corresponding bit in A unchanged 82

EOR 83 EOR 83

The EOR Instruction: LDA #A 9 EOR #OF Result: 1 O 1 O 1 The EOR Instruction: LDA #A 9 EOR #OF Result: 1 O 1 O 1 OO 1 OOOO 1111 ----1010 0110 (A) (M) Any 1 in the mask will invert the corresponding bit in A (so 1 becomes 0 and 0 becomes 1) Any 0 in the mask will leave the corresponding bit in A unchanged 84

Testing individual bits in a byte 85 Testing individual bits in a byte 85

Testing Individual Bits in a Byte: To test bit 2 of location $8 O Testing Individual Bits in a Byte: To test bit 2 of location $8 O LDA AND 8 O #O 4 byte to test mask OOOO O 1 OO 86

The Byte 7 6 5 4 3 2 1 0 0 0 ? 0 The Byte 7 6 5 4 3 2 1 0 0 0 ? 0 0 0 1 Hex 04 87

Testing Individual Bits in a Byte: eg - to test bit 2 of location Testing Individual Bits in a Byte: eg - to test bit 2 of location $8 O LDA AND 8 O #O 4 byte to test mask OOOO O 1 OO 88

Testing Individual Bits in a Byte: eg - to test bit 2 of location Testing Individual Bits in a Byte: eg - to test bit 2 of location $8 O LDA AND 8 O #O 4 byte to test mask OOOO O 1 OO $8 O contains $B 7 A 1 O 111 M OOOO O 1 OO ----OOOO O 1 OO Z flag =O 89

Testing Individual Bits in a Byte: eg - to test bit 2 of location Testing Individual Bits in a Byte: eg - to test bit 2 of location $8 O LDA AND 8 O #O 4 byte to test mask OOOO O 1 OO $8 O contains $B 7 A 1 O 111 M OOOO O 1 OO ----OOOO O 1 OO Z flag =O $8 O contains $69 A O 11 O 1 OO 1 M OOOO O 1 OO ----OOOO Z flag =1 90

The BIT Instruction: eg BIT (this is rather a funny instruction) LDA #O 1 The BIT Instruction: eg BIT (this is rather a funny instruction) LDA #O 1 mask for AND 8 O byte to test 7 6 5 4 3 2 1 0 0 1 N V Z is set by the result of the AND: 1 OO 1 OOOO 1 ----OOOO 1 ie non-zero so Z =O 91

Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF ORA Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF ORA #9 O EOR #8 O EOR #FF 92

Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF Result Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF Result is: OOOO OO 11 O 3 ORA #9 O EOR #8 O EOR #FF 93

Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF Result Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF Result is: OOOO OO 11 O 3 ORA #9 O Result is: 1 OO 11 93 EOR #8 O EOR #FF 94

Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF Result Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF Result is: OOOO OO 11 O 3 ORA #9 O Result is: 1 OO 11 93 EOR #8 O Result is: OOO 11 13 EOR #FF 95

Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF Result Logical instructions - Example: LDA #33 Result is: OO 11 33 AND #OF Result is: OOOO OO 11 O 3 ORA #9 O Result is: 1 OO 11 93 EOR #8 O Result is: OOO 11 13 EOR #FF Result is: 111 O 11 OO EC 96

Shift and Rotate Instructions 97 Shift and Rotate Instructions 97

Shift and Rotate Instructions: ASL 98 Shift and Rotate Instructions: ASL 98

Shift and Rotate Instructions: ASL LSR 99 Shift and Rotate Instructions: ASL LSR 99

Shift and Rotate Instructions: ASL LSR ROL 100 Shift and Rotate Instructions: ASL LSR ROL 100

Shift and Rotate Instructions: ASL LSR ROL ROR 101 Shift and Rotate Instructions: ASL LSR ROL ROR 101

The ASL instruction: The bits in the byte are shifted one position to the The ASL instruction: The bits in the byte are shifted one position to the left A zero is shifted into bit O Bit 7 is shifted out into the carry flag C 7 0 0 eg ASL 42 ASL 21 OF ASL A New Addressing Mode! 102

The LSR instruction: The bits in the byte are shifted one position to the The LSR instruction: The bits in the byte are shifted one position to the right A zero is shifted into bit 7 Bit 0 is shifted out into the carry flag 7 0 C 0 eg LSR 42 LSR 21 OF LSR A 103

The ASL instruction: C 0 7 0 0 0 0 104 The ASL instruction: C 0 7 0 0 0 0 104

The ASL instruction: C 0 7 0 0 0 105 The ASL instruction: C 0 7 0 0 0 105

The ASL instruction: C 0 7 0 0 0 106 The ASL instruction: C 0 7 0 0 0 106

The ASL instruction: C 0 7 0 0 0 0 107 The ASL instruction: C 0 7 0 0 0 0 107

The ASL instruction: C 0 7 0 0 0 108 The ASL instruction: C 0 7 0 0 0 108

The ASL instruction: C 0 7 0 0 1 0 0 0 109 The ASL instruction: C 0 7 0 0 1 0 0 0 109

The ASL instruction: C 0 7 0 1 0 0 0 0 110 The ASL instruction: C 0 7 0 1 0 0 0 0 110

The ASL instruction: C 1 7 0 0 0 0 0 111 The ASL instruction: C 1 7 0 0 0 0 0 111

The ASL instruction: C 0 7 0 0 0 0 0 112 The ASL instruction: C 0 7 0 0 0 0 0 112

The ROL instruction: The bits in the byte are shifted one position to the The ROL instruction: The bits in the byte are shifted one position to the left The original value of the carry is shifted into bit O Bit 7 is shifted out into the carry flag C 7 0 113

The ROR instruction: The bits in the byte are shifted one position to the The ROR instruction: The bits in the byte are shifted one position to the right The original value of the carry is shifted into bit 7 Bit 0 is shifted out into the carry flag C 7 0 114

2 Byte Shift eg LSR 80 ROR 81 msb lsb 80 7 0 81 2 Byte Shift eg LSR 80 ROR 81 msb lsb 80 7 0 81 6 5 4 3 2 1 0 7 1 0 0 1 6 5 4 3 2 1 0 0 1 C 1 115

Jumping and Branching and Comparing 116 Jumping and Branching and Comparing 116

Unconditional Jump - JMP O 25 O O 251 O 253 O 255 --O Unconditional Jump - JMP O 25 O O 251 O 253 O 255 --O 257 | O 25 A | O 25 C --O 25 E O 261 CLC LDA ADC STA JMP LDA STA 4 O 41 42 O 25 E 8 O 81 FOFA 35 117

Conditional Branch Instructions: BNE BEQ Branch if not equal to zero Z =O Branch Conditional Branch Instructions: BNE BEQ Branch if not equal to zero Z =O Branch if equal to zero Z =1 BCC BCS Branch if carry clear Branch if carry set C =O C =1 BPL BMI Branch if plus (positive) Branch if minus (negative) N =O N =1 (BVC (BVS Branch if overflow clear Branch if overflow set V =O) V =1) 118

Conditional Branch Instructions: O 25 O LDA 8 O --O 252 BNE O 256 Conditional Branch Instructions: O 25 O LDA 8 O --O 252 BNE O 256 | O 254 LDA 81 --O 256 STA 82 O 258 BRK O 25 O O 251 O 252 O 253 O 254 O 255 O 256 O 257 O 258 A 5 8 O DO O 2 A 5 81 85 82 OO (LDA) (BNE) (LDA) (BRK) -4 -3 -2 -1 O +1 +2 +3 +4 = = = = = FC FD FE FF OO O 1 O 2 O 3 O 4 119

Delay Loop: 10 s O 4 OO O 4 O 2 O 4 O Delay Loop: 10 s O 4 OO O 4 O 2 O 4 O 4 O 4 O 6 O 4 O 8 O 4 OA O 4 OC O 4 OE O 41 O O 412 O 414 O 416 LDA STA STA DEC BNE RTS #12 82 #OO 8 O 81 8 O O 4 OA 81 O 4 OA 82 O 4 OA ; $12 = 18 decimal ; inner loop ; next loop ; outer loop 120

Comparing CMP CPX CPY 121 Comparing CMP CPX CPY 121

Compare Instructions: CMP CPX CPY Examples: CMP 8 O CMP 1234 CMP #O 3 Compare Instructions: CMP CPX CPY Examples: CMP 8 O CMP 1234 CMP #O 3 CPX 8 O CPX 1234 CPX #O 3 CPY 8 O CPY 1234 CPY #O 3 The Z and C flags are changed after a compare instruction as follows: A = M then Z =1 (BEQ will branch) A <> M then Z =O (BNE will branch) A >= M then C =1 (BCS will branch) A < M then C =O (BCC will branch) 122

To compare the contents of $5 O and $51: O 25 O O 252 To compare the contents of $5 O and $51: O 25 O O 252 O 254 O 256 O 258 O 25 A | O 26 O | O 27 O | O 28 O LDA CMP BEQ BCS BCC 5 O 51 O 26 O O 27 O O 28 O first number second number branch if first=second branch if first>second branch if firstsecond here if first

Loops and Indexed addressing 124 Loops and Indexed addressing 124

Incrementing and Decrementing 125 Incrementing and Decrementing 125

Incrementing and Decrementing: Memory Locations: INC 8 O DEC 2 F INC O 412 Incrementing and Decrementing: Memory Locations: INC 8 O DEC 2 F INC O 412 DEC 12 BA Registers: INX DEX INY DEY 126

Car Mileometer 99 9 What happens if you drive forward one more mile? 127 Car Mileometer 99 9 What happens if you drive forward one more mile? 127

Car Mileometer 00 0 What happens if you reverse one mile? 128 Car Mileometer 00 0 What happens if you reverse one mile? 128

Decrementing X Instruction Value of X after instruction 04 DEX DEX O 3 O Decrementing X Instruction Value of X after instruction 04 DEX DEX O 3 O 2 O 1 OO FF FE FD (Z flag set) 129

Incrementing X Instruction Value of X after instruction FC INX INX FD FE FF Incrementing X Instruction Value of X after instruction FC INX INX FD FE FF OO 01 02 03 (Z flag set) 130

Looping 131 Looping 131

Loop Example: 80 O 25 O O 252 O 254 -O 255 | O Loop Example: 80 O 25 O O 252 O 254 -O 255 | O 257 | O 258 -O 25 A O 25 C O 25 E 81 LDA LDX CLC ADC INX CPX BNE STA BRK add the contents of locations 80 to 85 82 83 84 85 86 #OO A will hold sum X - loop counter 8 O, X Add next byte #O 6 O 255 8 A 87 Have we finished? If not continue Store the sum 132

Indexed Addressing 133 Indexed Addressing 133

Indexed Addressing: Zero Page, X ADC 8 O, X Zero Page, Y LDX Absolute, Indexed Addressing: Zero Page, X ADC 8 O, X Zero Page, Y LDX Absolute, X LDA 123 A, X Absolute, Y LDA 456 B, Y 8 O, Y 134

Delay Loop: 10 ms O 3 OO O 3 O 2 O 3 O Delay Loop: 10 ms O 3 OO O 3 O 2 O 3 O 4 O 3 O 5 O 3 O 7 O 3 O 8 O 3 OA LDY LDX DEX BNE DEY BNE RTS #OA; outer loop 1 O times #C 8; inner loop 2 OO times O 3 O 4 O 3 O 2 135

Delay Loop: 10 s O 4 OO O 4 O 2 O 4 O Delay Loop: 10 s O 4 OO O 4 O 2 O 4 O 4 O 4 O 6 O 4 O 8 O 4 OA O 4 OC O 4 OE O 41 O O 412 O 414 O 416 LDA STA STA DEC BNE RTS #12 82 #OO 8 O 81 8 O O 4 OA 81 O 4 OA 82 O 4 OA ; $12 = 18 decimal ; inner loop ; next loop ; outer loop 136

The NOP Instruction NOP does nothing 1 byte 2 clock cycles 137 The NOP Instruction NOP does nothing 1 byte 2 clock cycles 137

Subroutines and the Stack 138 Subroutines and the Stack 138

Subroutines: 0200 LDA 94 AND #07 JSR 0500 0207 LDA 94 ORA #80 JSR Subroutines: 0200 LDA 94 AND #07 JSR 0500 0207 LDA 94 ORA #80 JSR 0500 LDA 80 AND #0 F RTS 020 E LDX #08 JSR 0500 0213 STA 60, X DEX | 139

Subroutines: JSR 0500 RTS 140 Subroutines: JSR 0500 RTS 140

The Stack: SP 01 FF A 1 35 01 FF 01 FE 29 01 The Stack: SP 01 FF A 1 35 01 FF 01 FE 29 01 FD 81 01 FC 12 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 141

Push and Pull Instructions: Register A: PHA PLA store on stack get from stack Push and Pull Instructions: Register A: PHA PLA store on stack get from stack Flag Register: PHP PLP store on stack get from stack 142

Subroutines 0250 0262 * SP LDA #30 STA 51 CLC ADC #42 LSR A Subroutines 0250 0262 * SP LDA #30 STA 51 CLC ADC #42 LSR A 0400 0413 JSR 0500 STA 9 A LSR A STA 3 B RTS C MP #05 BNE 0294 JMP 0280 LDA 50 STA 62 ROR 7 E LDA #30 STA 51 CLC ADC #42 LSR A CMP #05 BNE 0294 JMP 0280 LDA 50 STA 62 0500 LSR A STA 6 F STA 77 RTS AA F 3 01 FF 01 FE 29 01 FD 81 01 FC 12 JSR 0400 CMP #05 BNE 0294 JMP 0280 LDA 50 ADC #42 LSR A LDA #30 STA 51 CLC ADC #42 LSR A 01 FF 01 FB 7 B 01 FA 5 D 01 F 9 * Before First JSR 143

The Stack: SP 01 FF A 1 35 01 FF 01 FE 29 01 The Stack: SP 01 FF A 1 35 01 FF 01 FE 29 01 FD 81 01 FC 12 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 144

The Stack: 01 FC 12 Store the value AA on the stack 01 FD The Stack: 01 FC 12 Store the value AA on the stack 01 FD 81 01 FF 01 FE 29 SP A 1 35 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 145

The Stack: 01 FC 12 Store the value AA on the stack 01 FD The Stack: 01 FC 12 Store the value AA on the stack 01 FD 81 01 FE 01 FF 01 FE 29 SP AA 35 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 146

The Stack: 01 FC 12 Store the value F 3 on the stack 01 The Stack: 01 FC 12 Store the value F 3 on the stack 01 FD 81 01 FE 01 FF 01 FE 29 SP AA 35 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 147

The Stack: 01 FC 12 Store the value F 3 on the stack 01 The Stack: 01 FC 12 Store the value F 3 on the stack 01 FD 81 01 FD 01 FF 01 FE 29 SP AA F 3 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 148

The Stack: 01 FC 12 The Stack pointer always contains the address of the The Stack: 01 FC 12 The Stack pointer always contains the address of the next free location 01 FD 81 01 FD 01 FF 01 FE 29 SP AA F 3 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 149

The Stack: 01 FC 12 Get a byte from the stack 01 FD 81 The Stack: 01 FC 12 Get a byte from the stack 01 FD 81 01 FD 01 FF 01 FE 29 SP AA F 3 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 150

The Stack: 01 FC 12 Get a byte from the stack The Stack Pointer The Stack: 01 FC 12 Get a byte from the stack The Stack Pointer is first incremented to point to the last value stored 01 FD 81 01 FE 01 FF 01 FE 29 SP AA F 3 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 151

The Stack: We get the value F 3 the last value stored 01 FE The Stack: We get the value F 3 the last value stored 01 FE is now the next free location 01 FC 12 Get a byte from the stack: 01 FD 81 01 FE 01 FF 01 FE 29 SP AA F 3 01 FB 7 B 01 FA 5 D 01 F 9 | 0100 152

What happens when a subroutine is called: before JSR AA 01 FF 0260 JSR What happens when a subroutine is called: before JSR AA 01 FF 0260 JSR 0500 0263 LDA #00 0500 LDX #03 0502 TAY 0503 RTS F 3 29 01 FE 01 FD 81 SP 01 FF 01 FC 12 01 FB 7 B 01 FA 5 D 01 F 9 153

What happens when a subroutine is called: after JSR 01 FD 0260 JSR 0500 What happens when a subroutine is called: after JSR 01 FD 0260 JSR 0500 0263 LDA #00 0500 LDX #03 0502 TAY 0503 RTS 01 FF 01 FE 01 FD 81 SP 02 62 29 01 FC 12 01 FB 7 B 01 FA 5 D 01 F 9 154

What happens when a subroutine is called: after RTS 01 FF 0260 JSR 0500 What happens when a subroutine is called: after RTS 01 FF 0260 JSR 0500 0263 LDA #00 0500 LDX #03 0502 TAY 0503 RTS 01 FF 01 FE 01 FD 81 SP 02 62 29 01 FC 12 01 FB 7 B 01 FA 5 D 01 F 9 155

Interrupts 156 Interrupts 156

Interrupts Main Program: Interrupt occurs here LDA #30 STA 51 CLC ADC #42 LSR Interrupts Main Program: Interrupt occurs here LDA #30 STA 51 CLC ADC #42 LSR A CMP #05 BNE 0294 JMP 0280 LDA 50 STA 62 ROR 7 E LDA #30 STA 51 CLC ADC #42 LSR A CMP #05 BNE 0294 JMP 0280 LDA 50 STA 62 Interrupt Routine: PHA LDA #33 STA 51 LDA A 000 STA 80 LDA A 001 STA 81 INC 9 A DEC 9 B PLA RTI When an interrupt occurs, the return address is stored on the stack, in the same way as for a subroutine call. The contents of the flag register is also stored on the stack. 157

5 v 10 K 6502 Interrupt inputs: ___ IRQ ___ NMI 0 v ___ 5 v 10 K 6502 Interrupt inputs: ___ IRQ ___ NMI 0 v ___ RES 6502 microprocessor 158

6502 Vectors: ___ NMI ___ RES ___ IRQ $FFFA + $FFFB $FFFC + $FFFD 6502 Vectors: ___ NMI ___ RES ___ IRQ $FFFA + $FFFB $FFFC + $FFFD $FFFE + $FFFF 159

Vectors: Memory 7 0 IRQ MSB IRQ LSB RES MSB RES LSB NMI MSB Vectors: Memory 7 0 IRQ MSB IRQ LSB RES MSB RES LSB NMI MSB NMI LSB FFFF FFFE FFFD FFFC FFFB FFFA 160

6502 Programmer’s Model 7 Microprocessor 7 Memory 0 FFFF 0 A X 8 Y 6502 Programmer’s Model 7 Microprocessor 7 Memory 0 FFFF 0 A X 8 Y PC 00000001 SP 15 NV-BDIZC PS STACK PAGE ZERO 0200 01 FF 0100 00 FF 0000 161

The Interrupt Flag I: CLI set I = O - Enable SEI set I The Interrupt Flag I: CLI set I = O - Enable SEI set I = 1 - Disable IRQ interrupts 162

Saving registers used in interrupt routines: PHA TXA PHA TYA PHA | {interrupt | Saving registers used in interrupt routines: PHA TXA PHA TYA PHA | {interrupt | PLA TAY PLA TAX PLA RTI ; save A (no need to save the flags) ; save X ; save Y routine instructions} ; restore Y ; restore X ; restore A 163

The BRK Instruction: BRK 164 The BRK Instruction: BRK 164

6502 Programmer’s Model 7 Microprocessor 7 Memory 0 FFFF 0 A X 8 Y 6502 Programmer’s Model 7 Microprocessor 7 Memory 0 FFFF 0 A X 8 Y PC 00000001 SP 15 NV-BDIZC PS STACK PAGE ZERO 0200 01 FF 0100 00 FF 0000 165

Checking the B BRK Flag: PHA PHP PLA AND BNE | save A get Checking the B BRK Flag: PHA PHP PLA AND BNE | save A get flags in A #1 O O 81 O test bit 4 (B flag) if set it was BRK interrupt else continue with normal IRQ | input | routine from external RTI 166

On Tuesday we did: Indirect Addressing 167 On Tuesday we did: Indirect Addressing 167

Direct and Indirect addressing: 2340 2341 2342 2343 2344 2345 2346 One of these Direct and Indirect addressing: 2340 2341 2342 2343 2344 2345 2346 One of these houses contains the treasure (the data) If I know the address (2342) then. . . 168

Direct addressing: 2340 2341 2342 2343 2344 2345 2346 Treasure! I go directly to Direct addressing: 2340 2341 2342 2343 2344 2345 2346 Treasure! I go directly to address 2342 where the data (the treasure) is stored 169

Direct and Indirect addressing: 2340 2341 2342 2343 2344 2345 2346 This time I Direct and Indirect addressing: 2340 2341 2342 2343 2344 2345 2346 This time I don’t know where the treasure is stored, but I do know that I can find the address by going to another house (2346) So I go to address 2346 where. . . 170

Indirect addressing: 2340 2341 2342 2343 2344 2345 2346 2342 I get the data Indirect addressing: 2340 2341 2342 2343 2344 2345 2346 2342 I get the data - the address where the treasure is address 2342. I can then go to address 2342 and get the data there the treasure. 171

Indirect addressing: 2340 2341 2342 2343 2344 2345 2346 Treasure! I go to address Indirect addressing: 2340 2341 2342 2343 2344 2345 2346 Treasure! I go to address 2342 where the data (the treasure) is stored 172

Indirect Addressing gives us the address of the address that we want 173 Indirect Addressing gives us the address of the address that we want 173

Indirect JMP 174 Indirect JMP 174

Direct JMP: JMP O 8 O 7 Indirect JMP: JMP (O 8 O 7) Direct JMP: JMP O 8 O 7 Indirect JMP: JMP (O 8 O 7) 175

Memory 7 0 12 34 0808 0807 Indirect JMP: JMP (O 8 O 7) Memory 7 0 12 34 0808 0807 Indirect JMP: JMP (O 8 O 7) results in a jump to location $1234 176

Indexed Indirect Addressing 177 Indexed Indirect Addressing 177

Indexed indirect or pre-indexed indirect addressing: (IND, X) eg LDA (8 O, X) Indirect Indexed indirect or pre-indexed indirect addressing: (IND, X) eg LDA (8 O, X) Indirect indexed or post-indexed indirect addressing: (IND), Y eg LDA (8 O), Y Both these addressing modes are only available with zero page addresses for IND 178

Indexed indirect or pre-indexed indirect addressing: For (IND, X) addressing, the current value of Indexed indirect or pre-indexed indirect addressing: For (IND, X) addressing, the current value of X is added to IND. This gives the address of the address to be used. Indirect indexed or post-indexed indirect addressing: For (IND), Y addressing, IND gives the address of the address to be indexed. This address is then indexed by Y giving the address to be used. 179

(IND, X) example: If: The X register contains 5 Location $85 contains $78 Location (IND, X) example: If: The X register contains 5 Location $85 contains $78 Location $86 contains $56 and the following instruction is executed: LDA (8 O, X) then the contents of X is added to $8 O giving $85. The address actually used is found in locations $85 and $86 ie $5678. So that using these values, LDA (8 O, X) LDA 5678 is equivalent to 180

Indexed Indirect Addressing (I, X) Memory 7 eg 0 if X = 5 LDA Indexed Indirect Addressing (I, X) Memory 7 eg 0 if X = 5 LDA (80, X) result: LDA (85) 56 78 86 85 LDA 5678 181

(IND), Y example: If: The Y register contains 7 Location $8 O contains $34 (IND), Y example: If: The Y register contains 7 Location $8 O contains $34 Location $81 contains $12 and the following instruction is executed: LDA (8 O), Y then the address stored in $8 O and $81 is to be indexed by Y, equivalent to LDA 1234, Y. Final address=$1234 + Y (7) = $123 B. Using these values, LDA (8 O), Y is equivalent to 123 B 182

Indexed Indirect Addressing (I), Y Memory 7 eg 0 if Y = 7 LDA Indexed Indirect Addressing (I), Y Memory 7 eg 0 if Y = 7 LDA (80), Y result: LDA 1234, Y 12 34 81 80 LDA 123 B 183

Indexed Addressing: LDA 0600, X range of X is 00 - FF so this Indexed Addressing: LDA 0600, X range of X is 00 - FF so this instruction can address locations 0600 - 06 FF Indexed Indirect Addressing: 7 0 LDA (20), Y Using just Y this instruction can address locations 0600 - 06 FF BUT 06 00 21 20 184

Indexed Addressing: LDA 0600, X range of X is 00 - FF so this Indexed Addressing: LDA 0600, X range of X is 00 - FF so this instruction can address locations 0600 - 06 FF Indexed Indirect Addressing: 7 0 LDA (20), Y Using just Y this instruction can address locations 0600 - 06 FF BUT Location 21 can then be incremented so the instruction will then address locations 0700 -07 FF. So we can address as much of memory as we want to. 07 00 21 20 185

Input/Output Programming Using the 6522 VIA 186 Input/Output Programming Using the 6522 VIA 186

The VIA: 187 The VIA: 187

Microprocessor System Memory Map: 7 0 FFFF ROM I/O RAM 0000 188 Microprocessor System Memory Map: 7 0 FFFF ROM I/O RAM 0000 188

Microprocessor System Memory Map: 7 0 FFFF ROM I/O LDA 0300 LDA F 000 Microprocessor System Memory Map: 7 0 FFFF ROM I/O LDA 0300 LDA F 000 LDA A 000 RAM 0000 189

The VIA: VIA __ CS 190 The VIA: VIA __ CS 190

The VIA: A 0 A 1 A 2 VIA A 3 __ CS 191 The VIA: A 0 A 1 A 2 VIA A 3 __ CS 191

The VIA: A 0 A 1 A 2 VIA A 3 __ CS A The VIA: A 0 A 1 A 2 VIA A 3 __ CS A 0 to A 3 so 0000 -1111 ie 16 locations 192

VIA Registers (AIM addresses): A 000 A 001 A 002 A 003 A 004 VIA Registers (AIM addresses): A 000 A 001 A 002 A 003 A 004 A 005 A 006 A 007 A 008 A 009 A 00 A A 00 B A 00 C A 00 D A 00 E A 00 F Port B Data Register (DRB) Port A Data Register (DRA) Port B Data Direction Register (DDRB) Port A Data Direction Register (DDRA) Timer 1 LSB Timer 1 MSB Timer 1 Timer 2 LSB Timer 2 MSB Shift Register Auxiliary Control Register (ACR) Peripheral Control Register (PCR) Interrupt Flag Register (IFR) Interrupt Enable Register (IER) Port A Data Register (No handshake) 193

The VIA: PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 The VIA: PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PA 6 PA 7 VIA Port A CA 1 CA 2 PB 0 PB 1 PB 2 PB 3 PB 4 PB 5 PB 6 PB 7 Port B CB 1 CB 2 194

Simple use of the VIA: LDA #00 STA A 003 LDA #FF STA A Simple use of the VIA: LDA #00 STA A 003 LDA #FF STA A 002 Set Port A as all inputs Data direction register A Set Port B as all outputs Data direction register B LDA A 001 STA A 000 JMP Read Port A Write to Port B 195

The VIA: 10 K 5 v PA 0 0 v VIA Buffer 220 PB The VIA: 10 K 5 v PA 0 0 v VIA Buffer 220 PB 0 0 v 196

Using the CB 2 Control Line: PCR 7 PCR 6 PCR 5 Mode: for Using the CB 2 Control Line: PCR 7 PCR 6 PCR 5 Mode: for operation of CB 2 control line 0 0 0 Input: IFR 3 set by neg edge on CB 2, cleared by read or write to DRB 0 0 1 Input: IFR 3 set by neg edge on CB 2, NOT cleared by read/write to DRB 0 1 0 Input: IFR 3 set by pos edge on CB 2, cleared by read or write to DRB 0 1 1 Input: IFR 3 set by pos edge on CB 2, NOT cleared by read/write to DRB 1 0 0 Output: CB 2 low on write to DRB, CB 2 high by active edge on CB 1 1 0 1 Output: CB 2 low for one clock cycle following write to DRB 1 1 0 Output: CB 2 held low 1 1 1 Output: CB 2 held high 197

Handshaking: Microprocessor system and a Printer CB 1 READY CB 2 STROBE PB 0 Handshaking: Microprocessor system and a Printer CB 1 READY CB 2 STROBE PB 0 DO PB 1 D 1 PB 2 D 2 PB 3 D 3 PB 4 D 4 PB 5 D 5 PB 6 D 6 PB 7 D 7 VIA Printer 1. Byte is output from VIA on Port B 2. STROBE pulse is output on CB 2 3. Program waits for READY line to go High 198

VIA Timer: MSB LSB C 3 50 C 350 = 50, 000 ie 50 VIA Timer: MSB LSB C 3 50 C 350 = 50, 000 ie 50 ms if system clock is 1 MHz 199

The End ! 200 The End ! 200