Meeting Agenda u Introduction 9 00 -9 30

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Meeting Agenda u Introduction (9: 00 -9: 30) s Application driver focus of the GSRC, and implications for C. A. D. Theme status and futures u GTX (Technology Extrapolation) s Tool status and current development (Mike Oliver) (9: 30 -9: 45) s Recent work (9: 45 -10: 45) t t t s DRAM (Michael Wang (Dai)) Interconnect modeling (Xuejue Huang (King)) Global signaling (Himanshu Kaul (Sylvester)) What can GTX do to support drivers? (10: 45 -11: 30) u Bookshelf (CAD-IP Reuse) s Status and summary of recent work (Igor Markov) (11: 30 -noon) s Open Access (1: 00 -2: 00) s What can Bookshelf do to support drivers = vertical benchmarks++ ? (2: 00 -2: 45) u Roadmap for C. A. D. Theme + action items (until adjourn) 1

C. A. D. Initiatives u Specification Gap: e. g. , What will be the critical design problem? s s GTX models include canned optimizations = canned design space explorations u Development and Delivery Gap: e. g. , How to deploy DT better/faster? s Bookshelf u Measurement Gap: e. g. , Did achievable design improve? s Metrics s Definition of success u (Next up: Education? Measuring research process? ) u. Shared Context Is A Force Multiplier 2

Ubiquitous Node Design Specifications u Major Constraints (depending upon the application) s Cost: < 1 $ s Size: 1 mm 3 … 1 cm 3 s Power: between 10 m. W and 100 m. W (depending upon ubiquitousness and mobility) u Hybrid s Mixed-signal (sensing, air interface, power train) s Mixed technology (passives, MEMs) u Limited flexibility s Downloadable and adaptable application layer s Parameterizable interfaces 3

Perspective: Single-Chip Bluetooth Radio (Alcatel, 2001) 4

Pico. Node V 3 Architecture SIF = sensor interface 16 k. B CODE 4 k. B XDATA 256 DATA Chip Supervisor DW 8051 Flash Storage Serial sfrbus or membus? 20 MHz Clock Source Flash. IF SIF ADC MAC Voltage Supply SIF Local. HW Serial GPIO ADC PHY Sensor 1 Sensor 2 Prg. Thresh 0 Prg. Thresh 1 User Interface OOK Receiver Tx 0 Tx 2 OOK Transmitter 5

Challenge: Packaging “Smart Dust” mote Combines sensing, computation, optical communication, and solar array [K. Pister (UCB)] 6

Home Networking Driver u System: 10 GOps/s s 2 -3 types of I/O ports (PCI, USB, Ethernet) s Bus speed: 100 -200 MHz s Bus bandwidth: 2 -4 Gb/s s Memory speed: 100 -400 MHz u Core Processor: s Transistors: 5 -60 Million s Clock frequency: 500 MHz-1 GHz s Area: 100 -250 mm 2 s Power: >= 50 W 7

Specification of a Home Network 2005 u System: (18 GOps/s) s s Area: 10 -50 mm 2 , Power: <5 W s Bus speed: 400 -800 MHz s Bus bandwidth: 10 -20 Gb/s s Memory speed: 400 MHz-1 GHz s u 4 -5 types of I/O ports (PCI, USB, Ethernet, 802. 11, IEEE 1394, Bluetooth) Analog part ? Core Processor: s s Clock frequency: 500 MHz-1 GHz s Area: 100 -200 mm 2 s u Transistors: 5 -50 Million Power: < 20 W Network Processor: s Transistors: 50 -100 Million s Clock frequency: 200 -800 MHz (2 -10 PE’s) s Area: 100 -300 mm 2 s Power: < 10 W 8

Home Network in 2005 laptop Broadband modem (cable/x. DSL) Ethernet Embedded gateway 802. 11 HDTV IEEE 1394 Bluetooth webpad Ethernet Printer pc 9

Design Challenge: What Does the Military Want A Modern Fighter/Attack Radar To Do? as: such Background*: Contribute to… by providing… Attack Mission Target acquisition Target discrimination Weapon delivery support Detect, ID, locate friend or foe AMRAAM, JDAM, etc. Survivability Situational awareness Low observability EMCON and LPI Electronic attack Navigation aid Air & surface Low RCS Power management Spoofing, jamming TF/TA Supportability High availability Small logistics footprint Long MTBF, short MTTR Min. spares kit, test set Affordability Low cost of ownership No DMS problems Low impact on the aircraft Weight, cooling * Source: Mike Lucas, Northrop Grumman such as: These broad objectives were set forth by Mike Lucas (Northrop Grumman) in his DARPA presentation last December 10

The Future Design Challenge: A Digital ESA Radar Digital ESA A/D Aircraft power Power Supply Array Driver A/D Digital Beam Former A/D BSC Exciter . . . Processor/ Controller to Mission Computer * Source: Mike Lucas 11

Digital Radar Technology Directions u AESA/Receiver s More Channels: 1000 s Higher A/D Sampling Rates: 1 Gsps and Above s Higher Dynamic Range: 14 -15 bits u Beam Forming s Higher Signal Processing Throughputs: 100 of TFLOPS s Continued Power Constraints: Needs 100 GFLOPS/Watt s Optimized Mission Specific Processing, Low Cost ASICs s High AESA to Beam Former Bandwidth: Multi Tbps u Signal Processing s Parallel Processing Architectures with High Bisection Bandwidth s Increased Use of COTS and Standards s Increased Software Reuse * Source: Mike Lucas 12

Drivers, GSRC, and C. A. D. Theme u GSRC is now managed by DARPA design drivers are key s Require quantified proofs of impact s Also, quarterly progress reports, etc. u C. A. D. Theme status s + “Living Roadmap”: high perceived impact and value s + Research not centrally managed, aligned freedom to do as we please s + Funding this year was stable for everyone s - Bookshelf fairly dormant, external participation only for $ s - Metrics dormant (but, progressing in Cadence) s - Integration with other Themes, FRCs is minimal t t Fabrics, Power/Energy, System-Level integrations should be deep/active Integrations with Interconnect, MSD, C 2 S 2 focus centers should be deep/active u Theme processes will have to change s Roadmap, concrete plans, quarterly progress report roll-up s Alignment with theme work s Conference calls, … (other mechanisms) 13

Living Roadmap (of Application Drivers) u Network, telecommunications, embedded computing systems s Synchronous buses 1 Gbps, differential signaling 10 Gbps Network, optical interfaces have multipliers of 10 x, 4 x (faster than device density, speed) Train wrecks: chip-to-package and system-level interconnects (materials, signaling standards, implementation costs), power, design TAT, cost u Appropriate metrics are “non-traditional”: density, cost, performance, power, and RAS (reliability, availability, and serviceability) s s Density: connections and bandwidth per cm(2, 3) , watts/m 3 Performance: How many interconnect/cm(2, 3)? How long are traces? What types of signals, and what voltage levels, will meet signaling rate needs? Cost: decompositions (mother, switch/routing, control, port interface, application), and dimensions (per (g. E, FC, DWDM, …) port, Gbps, MIPS, $ …) RAS: unintentionally / intentionally (for func) dropped bits/packets dropped, failure rates u Many models to build and integrate: SOC integration (what is integratable, at what cost), analog circuits/DT (how badly do these fail to scale), design quality and cost, power (circuits, multi-Vdd/Vt/tox / biasing, GALS/GSLA, …), manufacturing interface (variability, NRE, 14 layout densities, …)

Bookshelf u Goal is to produce component-based, application-specific design methodologies and flows s s How will the methodology space be explored, and flows prototyped? Where are the reusable components? u Open-source (understandable, reusable), malleable DT components s Centered on back end, completely missing AMS capabilities, … u Common data model and access mechanism (and repository? ) s Open. Access source code release u Design Drivers very close to vertical benchmarks (= existing Bookshelf slot) s s Recent overtures from IBM, LSI w. r. t. Open. Access, working vertical benchmarks Potential work with Fabrics on snap-on flows, etc. u. KEY: Common DT Infrastructure 15

Metrics u Goal: measure and improve s Systems s Processes u Relevant system attributes / metrics u System value u System cost (design, production) s From system ROI, have a platform from which to evaluate technology ROI u Technology cost (research, advanced research, development, …) u Supporting technologies / infrastructures (data mining, parameter identification, model fitting) u Other: Research process s What is the impact of FCRP ? (# newspaper articles? # papers? Coauthorship statistics? Survey results? Scientific health of 16