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MAPS R&D program for SVT Layer 0 Giuliana Rizzo for the Pisa Group V MAPS R&D program for SVT Layer 0 Giuliana Rizzo for the Pisa Group V Super. B Work. Shop Paris – May 9, 2007 G. Rizzo Super. B Workshop - Paris - May 9, 2007 1

Outline • Recent results on deep nwell (DNW) CMOS MAPS • R&D issues for Outline • Recent results on deep nwell (DNW) CMOS MAPS • R&D issues for CMOS MAPS: – – Fast readout architecture Sensor optimization Radiation hardness Mechanical issues covered in the next talk • R&D strategy G. Rizzo Super. B Workshop - Paris - May 9, 2007 2

CDR SVT Layer 0 • CDR: 2 options for Layer 0 design – Striplets CDR SVT Layer 0 • CDR: 2 options for Layer 0 design – Striplets option: mature technology, less robust against background occupancy. – CMOS MAPS options: more challenging technology, more robust against background occupancy. • Both cases: 8 modules @ r=1. 5 cm, 50 m pitch, material budget < 0. 5% X 0. • Background rate expected ~ 5 MHz/cm 2 (x 5 safety to be included) G. Rizzo Super. B Workshop - Paris - May 9, 2007 3

Layer 0 MAPS R&D issues • CMOS Monolithic Active Pixels (MAPS) are a very Layer 0 MAPS R&D issues • CMOS Monolithic Active Pixels (MAPS) are a very promising “new device” (granular, thin, quite rad hard), but so far never used in a real operating detector. • Extensive R&D needed – – Design trade off with Fast readout architecture monolithic pixels Sensor optimization Radiation hardness Mechanical issues: Sensor thinning, module design, light cooling … see next talk by S. Bettarini • CMOS MAPS is an option for the ILC vertex detector many aspects of the R&D are common G. Rizzo Super. B Workshop - Paris - May 9, 2007 4

CMOS MAPS electronics & interconnects epitaxial layer Principle of Operation: • Electrons generated by CMOS MAPS electronics & interconnects epitaxial layer Principle of Operation: • Electrons generated by the incident particle in the undepleted epitaxial layer move by thermal diffusion. – Q ~ 80 e-h/ m -> Signal ~ 1000 e • Signal collected by the n-well/p-epi diode Advantages: • • • Same substrate for detector-readout: ® less material in the detection region (thin down to ~ 50 um) Sensor faster and more rad hard than CCDs CMOS deep submicron process – – low power consumption and fabrication costs electronics intrinsically radiation hard G. Rizzo (~ 10 m thick) substrate (~ 300 m thick) Developed for imaging applications, recently proven to work well also for charged particles: good efficiency & resolution performance measured Lots of MAPS R&D in many places with a “conventional” approach: • Charge-to-voltage conversion provided by sensor capacitance -> small collecting electrode -> small single pixel signal • Extremely simple in-pixel readout configuration (3 NMOSFETs) -> sequential readout -> readout speed limitation Super. B Workshop - Paris - May 9, 2007 5

Deep Nwell CMOS MAPS design New approach in CMOS MAPS design to improve the Deep Nwell CMOS MAPS design New approach in CMOS MAPS design to improve the readout speed potential: APSEL chip series SLIM 5 Collaboration - INFN & Italian University • Full in-pixel signal processing realized exploiting triple well CMOS process PRE SHAPER DISC LATCH • Deep nwell (DNW) as collecting electrode Gain independent of the sensor capacitance collecting electrode can be extended • Area of the “competitive” nwells inside the pixel kept to a minimum: , they steel signal to the main DNW electrode. • Fill factor = DNW/total n-well area 0. 85 in the prototype test structures • Pixel structure compatible with data sparsification architecture to improve redout speed. G. Rizzo Deep nwell • competitive nwell Proof of principle with the first prototypes realized in 130 nm triple well CMOS process (STMicrolectronics) Super. B Workshop - Paris - May 9, 2007 6

APSEL series recent results 3 x 3 matrix, full analog • Starting from the APSEL series recent results 3 x 3 matrix, full analog • Starting from the triple well MAPS design 6 test chips produced • • 4 x 4 matrix with sparsified readout 8 x 8 matrix Sequential readout Better optimization of the front-end: Noise ENC = 50 e. Measurements with radioactive sources (90 Sr b, 55 Fe g) on 3 x 3 matrix with analog output: • Indications of small cluster size (1 -4 pixels) • Cluster Signal for MIP (Landau MPV) 700 e- S/N = 14 • Measurements on 8 x 8 matrix with digital output and sequential readout: • Residual capacitive coupling between the digital lines and the sensor (C~10 a. F !!!) is an issue: crosstalk effects observed. • Noise ENC = 50 e • Threshold dispersion reduced to ~ 100 e- (still to be improved) • Differential spectra with radioactive sources OK. – Inserted shielding with metal planes to cure the problem in the next chips in productions. G. Rizzo Super. B Workshop - Paris - May 9, 2007 7

3 x 3 matrix, full analog output APSEL 2 3 x 3 matrix: analog 3 x 3 matrix, full analog output APSEL 2 3 x 3 matrix: analog output 90 Sr electrons S/N=14 Cluster Multiplicity 1 Landau m. V 2 Hit pixels in 3 x 3 matrix Cluster seed Noise events properly normalized Cluster signal (m. V) • Noise ENC = 50 e • Indications of small cluster size (1 -2 pixels) • Cluster Signal for MIP (Landau MPV) 700 e S/N = 14 G. Rizzo Super. B Workshop - Paris - May 9, 2007 8

APSEL 2 8 x 8 matrix: digital output Noise scan: hit rate vs discriminator APSEL 2 8 x 8 matrix: digital output Noise scan: hit rate vs discriminator threshold 8 x 8 matrix digital output Sequential readout Noise Vthr Vth (m. V) Threshold dispersion ~ 100 e 90 Sr electrons: single pixel spectrum Spectrum from analog output Differential spectrum from digital output Noise (m. V) Average Noise ENC = 50 G. Rizzo e- Super. B Workshop - Paris - May 9, 2007 9

Readout Architecture for MAPS • Data-driven readout architecture with sparsification and timestamp information under Readout Architecture for MAPS • Data-driven readout architecture with sparsification and timestamp information under development. • Need to minimize in the active sensor area: – the logical blocks with pmos to minimize the competitive nwell area and preserve the collection efficiency of the DNW sensor. – digital lines for point to point connections scales with matrix dimensions – – – – Matrix subdivided in Macro. Pixel (MP=4 x 4) with point to point connection to the End Of Column Token pass logic scans for hits in the EOCs (stored list of hit MPs and relative timestamp) to start the redout of the corresponding MP. Pixel data from each read out MP are sent to the End Of Row and to the sparsification logic. Data output interface formats the output of the sparsification, associates the TS and sends data to output lines End Of Rows - EOR - to reduce cross talk with the sensor underneath. Sparsification MP MP MP End Of Columns - EOC - First small chip submitted in Nov 2006 (4 x 4 pixels). Larger prototypes (up to ~4 k pixels) in production in the next 6 months. Simulation under way to evaluate performance with the Super. B background rates. G. Rizzo Super. B Workshop - Paris - May 9, 2007 10

Pixel Cell optimization: Noise/Power • Noise dominated by sensor capacitance Equivalent noise charge (ENC) Pixel Cell optimization: Noise/Power • Noise dominated by sensor capacitance Equivalent noise charge (ENC) reference MAPS with N-well extension series contribution from the input device standalon e ROC series contribution from the PMOS current source biasing the input device parallel contribution from the feedback network • Optimization Goal: High signal efficiency = large collection electrode area but with small capacitance (small noise). 1. 2. Changes in the design of the analog part help reduce the DNW sensor area and capacitance substantially (about a factor 3) To keep the efficiency high extend DNW electrode with smaller capacitance nwell collecting electrodes (smaller total capacitance) • DNW has higher specific Cap w. r. t. standard nwell • Cdnpw ~ 7 x Cnwpe G. Rizzo Super. B Workshop - Paris - May 9, 2007 11

APSEL 3 Noise/power trade-off in Apsel 3 not Layout NWELL PWELL NWELL 50 m APSEL 3 Noise/power trade-off in Apsel 3 not Layout NWELL PWELL NWELL 50 m DEEP NWELL Collecting electrode completed DEEP 50 m APSEL 2 Shap er feedb ack Mi. M cap. (digital and MIM capacitors section not present) 50 m Shaper input Mi. M cap. 50 m G. Rizzo II III Detector capacitance [f. F] 460 140 140 Analog power dissipation [ W] 60 8 17 30 Input device drain current [ A] 30 5 12 20 16/0. 25 4/0. 25 10/0. 25 [email protected] ns [electrons rms] Final design sensor capacitance ~ 150 – 300 f. F I Input device dimensions [ m/ m] • Noise/power trade-off can take advantage of the substantial reduction in the sensor capacitance APSEL 2 42 40 30 25 Super. B Workshop - Paris - May 9, 2007 schematic simulations 12

Pixel Cell optimization: Signal • Developed a fast simulation of the device (ionization and Pixel Cell optimization: Signal • Developed a fast simulation of the device (ionization and diffusion) to optimize the sensor geometry (E. Paoloni) – Detailed device simulation (ISETCAD) gives similar results – Fair agreement among data and Fast Simulation – Need further tuning of the sensible parameters – – 90 Sr electrons - APSEL 2 data + Fast Simulation identifies low efficiency regions inside pixel Improve efficiency adding in these areas small satellite nwells connected to the main DNW electrode (low contribution to the total sensor capacitance) Satellite nwells in the surroundings of the competitive nwell very effective to increase the efficiency G. Rizzo Super. B Workshop - Paris - May 9, 2007 13

An example of sensor optimization • With APSEL 2 cell (left) Efficiency ~ 96% An example of sensor optimization • With APSEL 2 cell (left) Efficiency ~ 96% from simulation (pixel threshold @ 250 e- = 5 x. Noise) • Inefficient regions shown in red (pixel signal < 250 e-) • Cell optimized with satellite nwells (right) Efficiency ~ 99. 5% 3 x 3 MATRIX APSEL 2 pixel 3 x 3 MATRIX pixel optimized Competitive Nwells Satellite nwells connected to the DNW electrode DNW collecting electrode G. Rizzo Super. B Workshop - Paris - May 9, 2007 14

MAPS Radiation Hardness • Expected Background @ Layer 0: – Dose = 6 Mrad/yr MAPS Radiation Hardness • Expected Background @ Layer 0: – Dose = 6 Mrad/yr – Equivalent fluence = 6 x 1012 neq/cm 2/yr • CMOS redout electronics (deep submicron) rad hard • MAPS sensor - Radiation damage affects S/N Results from standard nwell MAPS prototypes • Non-ionizing radiation: bulk damage cause charge collection reduction, due to lower minority carrier lifetime (trapping) fluences ~ 1012 neq/cm 2 affordable, 1013 neq/cm 2 possible • Ionizing radiation: noise increase, due to higher diode leakage current (surface damage) OK up to 20 Mrad with low integration time (10 s) or T operation < 0 o C, or modified pixel design to improve it • • • Irradiation test performed on several MAPS prototypes, with standard nwell sensor, indicate application for Super. B is viable. DNW design could be even more rad hard APSEL chips will be irradiated by the end of 2007 G. Rizzo Super. B Workshop - Paris - May 9, 2007 15

SLIM 5 Collaboration • The SLIM 5 Collaboration has a quite detailed project plan SLIM 5 Collaboration • The SLIM 5 Collaboration has a quite detailed project plan to build a prototype of a thin silicon tracker (MAPS and thin silicon striplets modules) with LV 1 trigger capabilities (based on Associative Memories). – Important aspect of the project is to develop light mechanical and cooling structures for thin silicon modules to benefit of the very low material budget of the sensor itself. • Test of the prototype tracker in a test beam in 2008/2009 • Several Italian Institutes involved in the project: – Pisa (coordination), Pavia, Bergamo, Trieste, Torino, Trento, Bologna • R&D project supported by the INFN and the Italian Ministry for Education, University and Research. G. Rizzo Super. B Workshop - Paris - May 9, 2007 16

CMOS MAPS R&D Strategy • Reasonable S/N performance achieved with present pixel design • CMOS MAPS R&D Strategy • Reasonable S/N performance achieved with present pixel design • Need to demonstrate fast readout architecture implementation is possible with this technology: – Cure digital crosstalk (test structures in production) – Scalability of the architecture to large matrix (by end of 2007) – Chip Performance measurement with test beam (2008/2009) • Optmize S/N and power dissipation • Investigate Radiation tolerance • Explore new possibilities to improve MAPS performance, based on Vertical Integration (3 D Electronics) industrial process. G. Rizzo Super. B Workshop - Paris - May 9, 2007 17

MAPS chips production in 2007 • May ’ 07: APSEL 2_CT In test from MAPS chips production in 2007 • May ’ 07: APSEL 2_CT In test from Sett ‘ 07 – Test structures with metal shield to cure residual digital crosstalk. – Sensor geometry improved Matrix 32 x 8, 256 pixels, 50 50µm 2 • July ’ 07: APSEL 3 series In test from Nov 07 – Analog 3 x 3 matrices with new pixel design (Signal/Noise/Power optimized) – Digital 8 x 8 matrix with sequential readout – Digital 256 pixels matrix with data driven architecture (no sensor connected/sensor connected ) • Nov ’ 07: 1 k/4 k pixel matrix with data driven architecture – pixel as in APSEL 3 series – Use feedback from May ‘ 07 test chip to cure crosstalk – MAPS sensor for 2008/2009 testbeams G. Rizzo Super. B Workshop - Paris - May 9, 2007 18

Explore new pixel technology • Time to explore new pixel technology for SVT Layer Explore new pixel technology • Time to explore new pixel technology for SVT Layer 0. – Vertical Integration of thin chips is commercially available. • Can use MAPS readout electronics on a thin chip connected to high resistivity thin pixel sensor: – 3 D interconnection technology could be adopted – Improve S/N w. r. t. to CMOS MAPS: • pixels on high resistivity substrate are fully depleted • Signal proportional to sensor thickness • Noise reduced with the lower detector capacitance – Reduce power dissipation (trade off with noise reduction) – Sensor can be extremely radiation hard G. Rizzo Super. B Workshop - Paris - May 9, 2007 19

Backup G. Rizzo Super. B Workshop - Paris - May 9, 2007 20 Backup G. Rizzo Super. B Workshop - Paris - May 9, 2007 20

Layer 0 striplets R&D issues • Technology for Layer 0 baseline striplet design well Layer 0 striplets R&D issues • Technology for Layer 0 baseline striplet design well estabilshed – – – Double sided Si strip detector 200 m thick Existent redout chip (FSSR 2 - Bte. V) match the requirements for striplets redout with good S/N ~ 25. – Redout speed and efficiency not an issue with the expected background rate (safety factor x 5 included) Reduction in L 0 material budget (from 0. 45% 0. 35% X 0) with R&D on the connection between the silicon sensor and the redout electronics: • Interconnection critical given the high number of readout channels/module (~3000). Possible choices: – Multiple layers of Upilex with Cu/gold traces with microbonding (as in SVT) – Kapton/Al microcables with Tape Automated Bonding (as in ALICE experiment) • Mechanical details worked out in some detail: from module assembling up to final mounting on the beam pipe. See nex talk (S. Bettarini) G. Rizzo Super. B Workshop - Paris - May 9, 2007 21

Final Layer 0 (striplets) structure • Mechanical details worked out in some detail: from Final Layer 0 (striplets) structure • Mechanical details worked out in some detail: from module assembling up to final mounting on the beam pipe. 3 -D view r-f cross section G. Rizzo Super. B Workshop - Paris - May 9, 2007 22

Module Layer 0 (striplets): 3 D-view Carbon-Kevlar ribs End piece Striplets Si detector (fanout Module Layer 0 (striplets): 3 D-view Carbon-Kevlar ribs End piece Striplets Si detector (fanout cut-away) Buttons (coupling HDI to flanges) Upilex fanout chip G. Rizzo Hybrids Super. B Workshop - Paris - May 9, 2007 23

Placing the Layer 0 module on the flanges Semicircular flanges (cooling circuit inside) Places Placing the Layer 0 module on the flanges Semicircular flanges (cooling circuit inside) Places for Buttons Thermal Conductive wings G. Rizzo Super. B Workshop - Paris - May 9, 2007 24

The whole SVT: Layer 0 inside the Ba. Bar SVT G. Rizzo Super. B The whole SVT: Layer 0 inside the Ba. Bar SVT G. Rizzo Super. B Workshop - Paris - May 9, 2007 25

Layer 0 MAPS module Two silicon layers (up/down) placed on the mechanical support forming Layer 0 MAPS module Two silicon layers (up/down) placed on the mechanical support forming a ladder. Each chip: 12. 8 mm x 12. 8 mm. Al. N-Al. N Interface: 50 m of Conductive Glue (4 watt/m. K) Power: 20000 watt/m 2 on each Silicon surface Temperature (FEA results) • Inlet cooling liquid @ 10 °C G. Rizzo • DT = 8°C Super. B Workshop - Paris - May max 9, 2007 (H 20 Flow=0. 094 l / min 2. 5 m/sec) 26

APSEL series recent results • • Better optimization of the frontend: Noise ENC = APSEL series recent results • • Better optimization of the frontend: Noise ENC = 50 e. Measurements with radioactive sources (90 Sr b source, 55 Fe g source) on 3 x 3 matrix with full analog output: • Indications of small cluster size (1 -4 pixels) • Cluster Signal for MIP (Landau MPV) 700 e- S/N = 14 Measurements on a 8 x 8 matrix with digital output and sequential readout. Layout modifications in the APSEL 2 chip to cure the main source of the digital iterference with the analog circuit • Noise ENC = 50 e • Threshold dispersion reduced to ~ 100 e- (300 e- in the first chip, but still to be improved) • Differential spectra with radioactive sources similar to spectra obtained with the full analog information. Residual capacitive coupling between the digital lines and the sensor (C~10 a. F !!!) is an issue: crosstalk effects observed. – Shielding with metal planes inserted to cure the problem in the next chips in productions. G. Rizzo Super. B Workshop - Paris - May 9, 2007 27

Readout Architecture for MAPS • Data-driven readout architecture with sparsification and timestamp information under Readout Architecture for MAPS • Data-driven readout architecture with sparsification and timestamp information under development. No external trigger needed; suitable for LV 1 trigger system based on associative memories. – – – Matrix subdivided in Macro. Pixel (MP=4 x 4) with point to point connection to the End Of Column MP Logical OR of pixels inside the MP sent to End Of Column, which has the following functionality: – Associates relative Time. Stamp to each hit MP – Freeze the hit MP until readout is completed MP MP – Retains the list of hit MPs and the relative TS – Selects which MP to read Token pass logic scans for hits in the EOCs to start the redout End Of Columns Sparsification of the corresponding MP. - EOC Pixel data from each read out MP are sent to the End Of Row and to the sparsification logic. Need to minimize in the Data output interface formats the output of the sparsification, active area (pixel and MP) associates the TS and sends data to output lines • the logical blocks (to minimize the competitive First small chip in production (4 x 4 pixels, with MP=2 x 2). nwell area) Medium size prototype (~1 k pixels) in production by the End Of Rows - EOR - – end of 2007. Simulation under way to evaluate performance with the expected Super. B background rates. - Paris - May 9, 2007 G. Rizzo Super. B Workshop • digital lines (to avoid cross talk) 28

APSEL series • Starting from the triple well MAPS design 6 test chips produced APSEL series • Starting from the triple well MAPS design 6 test chips produced 3 x 3 matrix, full analog 4 x 4 matrix with sparsified readout 8 x 8 matrix Sequential readout • Readout Architecture data driven with sparsification and timestamp information is under development: – Simulation under way to evaluate performance with the expected Super. B background rates. – First small chip in production, medium size prototype in production by the end of 2007. • Residual capacitive coupling between the digital lines and the sensor (C~10 a. F !!!) is an issue: crosstalk observed. – Shielding with metal planes inserted to cure the problem in the next chips in productions. G. Rizzo Super. B Workshop - Paris - May 9, 2007 29

G. Rizzo Super. B Workshop - Paris - May 9, 2007 30 G. Rizzo Super. B Workshop - Paris - May 9, 2007 30