Main Memory Computer Science Engineering Department Arizona

Main Memory Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu. edu (480) 727 -7507 3/18/2018

Memory Technology q “Non-so-random” Access Technology: v Access time varies from location to location and from time to time v Examples: Disk, tape drive, CDROM q Random Access: Mem(address) data v “Random” is good: access time is the same for all locations v DRAM: Dynamic Random Access Memory Ø one transistor per cell Ø High density, low power, cheap, slow Ø Dynamic: need to be “refreshed” regularly v SRAM: Static Random Access Memory Ø 4 -6 transistors per cell Ø Low density, high power, expensive, fast Ø Static: content will last “forever” 1

A 16 X 4 SRAM Din 3 Din 2 Din 1 Din 0 Wr. En Precharge - Wr Driver + SRAM Cell SRAM Cell : : SRAM Cell - Sense Amp + Word 0 Address Decoder SRAM Cell A 0 - Sense Amp + Dout 3 Dout 2 Dout 1 Word 1 A 2 A 3 Word 15 Dout 0 2

Hitachi HM 62256 B SRAM 3

SRAM Cell Architecture q Write: v Drive bit lines (bit=1, bit=0) v Select row q Read: v Precharge C and C to Vdd v Select row v Cell pulls one line low v Sense amp on column detects difference between C and C 4

SRAM Read Operation q read cycle time -- trc q address access time – taa q CS to access time – tacs q OE to output valid -- toe 5

SRAM Write Operation q write cycle time – twc q end of write q write pluse width -- twp 6

DRAM q A grid of capacitors to hold data bits q To access a bit v row address strobe (RAS) – to transfer an entire row to sense amplifier v column address strobe (CAS) – to choose a specific cell v refresh – to recharge the capacitors Ø Every time a row is read and also done periodically q Example: 2 Mb DRAM = 256 K * 8 = 512 rows * 512 cols * 8 bits 512 cols 512 Plane 1 col Plane 0 One “Plane” of 256 Kb DRAM sense D 256 Kb DRAM 512 rows Plane 7 r o w addr cell array N bits D<7> D<1> D<0> 7

DRAM q 1 -transistor cell: data is stored in a capacitor q Read: read and recharge q Refresh: a dummy read to recharge the capacitor q DRAM (Read/Write) Cycle Time >> DRAM (Read/Write) Access Time Cycle Time Access Time Memory Bank 0 q Interleaving: bank 0 bank 1 1 st read CPU bank 2 2 nd read 3 rd read Memory Bank 1 Memory Bank 2 Memory Bank 3 8

Different DRAMs q Asynchronous DRAM q FPM (fast page mode) v for each RAS, consecutive CAS to access bits in the same row q EDO (extended data out) v overlap data output and the next CAS (pipelined) q SDRAM (synchronous) v interleaved (2 banks)– one is refreshing and the other can be accessed v synchronized to clock and burst mode (without CAS) q Example: Micron SDRAM (MT 48 LC 1 M 16 A 1) v dual 512 K*16 DRAM – 2048 rows by 256 columns v burst access with lengths 1, 2, 4, 8, and full page v auto precharge function – self-timed row precharge at the end of the burst sequence v auto refresh -- internal refresh counter for row addresses Ø tref = 64 ms (2048 auto refresh cycles every 64 ms), i. e. once every 31. 25 s 9

Micron MT 48 LC 1 M 16 A 1 Block Diagram q CLK, CKE (clock q q q enable) CS# (chip select) WE# (write enable), RAS#, CAS# BA (bank address) A 0 -A 10 (address) DQ 0 -DQ 15 (data I/O) DQML, DQMH (input/output mask) – mask low or high bytes when write or enable output when read 10

SDRAM Read Operation q SDRAM has been initiated and mode register is loaded q Active (RAS) and then Read (with A 10 high for auto precharge) q CAS latency: delay between read command the availability of the 1 st piece of output data v CL 2 or CL 3: 2 or 3 clock cycles q Timing parameters: v t. RCD : between Active and Read/Write (RAS and CAS) v t. RAS : between Active to Precharge v t. RC : between successive Active’s to the same bank v t. RRD : between successive Active’s to different banks 11

Read without Auto Pre-charge 12

DDR (Double Data Rate) SDRAM q Same memory core v identical addressing and command control, refresh requirements v different data interface q At a data rate twice of the clock frequency v The internal bus is twice of the width of the external bus v data capture at both edges q Source-synchronous interfaces: 13

DDR Read Operation q DQS: data strobe v bi-directional, by the controller for write and DRAM for read q Either one of the two words read can be ignored. q DQS is edge aligned with DQ (clocked out at the same internal signal 14

DDR Write Operation q DQS is center-aligned relative to DQ and is used to capture input data 15

DIMM q 184 -pin dual in-line memory module (DIMM) v 128 MB (16 Meg x 64), 256 MB (32 Meg x 64), or 512 MB (64 Meg x 64) v ECC (-- x 72) v 8 or 4 DRAM chips q Serial presence-detect (SPD) – a 256 bytes EEPROM v to identify the module type and various SDRAM organizations and timing parameters v I 2 C interface with the controller q Registered– for servers, router, etc. v To assure data integrity, use registers to latch address and command signals and one PLL clock buffer to adjust timing. q Unbuffered -- cost optimized for desktop PC q 200 -pin, small outline, dual in-line memory module (SODIMM) 16

SDRAM Configuration Example q Assume we have 4 MT 48 LC 32 M 8 A 2 chips v each one is with 8 Meg x 8 x 4 banks (256 M bits) v need 4 chips to make a memory of 32 -bit data q Addresses (10+2+13=25 bits) v banks: BA 0 -BA 1 (2) v Row: A 0 -A 12 (13) v Column: A 0 -A 9 (10) q CPU sends 32 -bit addresses v AD 0 -AD 1 to select a byte from a word v AD 2 -AD 11, i. e. column address, to select a word from a row v AD 12 -AD 24 as row address v AD 25 -26 connected to BA 0 -BA 1 (non-interleaved) v AD 27 -31 to select the SDRAM memory (to enable CS) 17

SDRAM Configuration Example Assume CPU reads q v one word from memory location 0 x 09050120 Ø v CS=0 x 01, Row=0 x 1050, Bank=0 b 00, Column=0 x 044 two words from memory location 0 x 09050184 Ø CS=0 x 01, row=0 x 1050, Bank=0 b 00, Column=0 x 061 Burst length=1, t. RCD =1. 6 clock periods, and CAS Latency=2 q clock T 0 T 1 T 2 T 3 T 4 T 5 command Active NOP Read (precharge) 0 x 044 0 x 061 0 x 062 address DQs 0 x 1050 data 1 data 2 T 6 data 3 18