Low Power RF/Analog Amplifier Design Tong Zhang Auburn University
Motivation and Design Objective • Motivation Design a low power CMOS LNA (Low-Noise Amplifier) Design Objective f 0 2. 4 GHz NF < 2. 5 d. B Vdd 2 V S 12 < -25 d. B Gain > 15 d. B
My Work • This Work 1. Design a 2. 4 GHz cascode CMOS LNA. 2. Design a low power CMOS LNA with comparable performance. 3. Comparison between the two LNAs.
Tools and Techniques • Tools Virtuoso Schematic Composer and Spectre Simulator from Cadence Design Systems, Inc. • Techniques 0. 13 µm CMOS process
Circuit Diagram Comparison Traditional CMOS LNA Low Power CMOS LNA
Schematic of Traditional CMOS LNA
Schematic of Low Power CMOS LNA
Circuit Description • Traditional CMOS LNA 1. A inductance network (Lg, Ls ) is used for are used for input matching. 2. A RLC filter network (Lout, Cout, Rout ) is used for selecting the output frequency. 3. Vg 1 is biased at 0. 53 V; Vg 2 is biased at 1. 7 V; Vdd is biased at 2 V.
Circuit Description (cont’) • Low Power CMOS LNA 1. M 2 and P 1 operates as inverter-type amplifier stages to make LNA high linearity due to its symmetric structure. 2. C 1 couples the ac signal amplified by M 1 to M 2, while the source of M 2 is bypassed by C 2. 3. 3. Vg 1 is biased at 0. 5 V; Vg 2 is biased at 1. 3 V; Vdd is biased at 2 V.
Simulation Result • Input reflection coefficient (S 11) • output reflection coefficient (S 22) Traditional CMOS LNA Low Power CMOS LNA
Simulation Result (cont’) • Power gain(S 21) • noise figure (NF) Traditional CMOS LNA Low Power CMOS LNA
Simulation Result (cont’) • Reverse isolation(S 12) S 12=-40 d. B <-20 S 12=-49. 3 d. B<-20 Traditional CMOS LNA Low Power CMOS LNA
Simulation Result Summary Traditional LNA Low Power LNA Gain (S 21) 20 d. B 22 d. B NF 1. 7 d. B 2. 8 d. B S 12 -40 d. B -49 d. B Power 7. 23 m. W 4. 3 m. W
Power Consumption Traditional CMOS LNA P = Idd x Vdd = 3. 668 m. A x 2 V = 7. 23 m. W Low Power CMOS LNA P = Idd x Vdd = 2. 147 m. A x 2 V = 4. 3 m. W Power Reduction = 41. 5%
Conclusion Highlights • A current reuse technique is used to decrease power dissipation with increasing amplifier transconductance for the LNA. In my project, for nearly the same power gain, by decreasing gates bias we get 41. 5% power reduction • An inverter-type amplifier which has a symmetric structure is used to achieve high linearity for the LNA (not discussed)
Conclusion (cont’) What need to improve? • Input impedance was not well matched, which means the ac signal of the input will not be able to be fully delivered to the output. • Noise figure shows that the noise of output is a little bit large. A different input matching as well as output matching topology may improve the efficiency and minimize noise of the LNA
Reference • Ickjin Kwon and Hyungcheol Shin , “Design of a New Low-Power 2. 4 GHz CMOS LNA” , Journal of the Korean Physical Society, Vol. 40, No. 1, Jan. 2002, pp. 4 -7. • John D. Cressler and Guofu Niu, “Silicon-Germanium Heterojunction Bipolar transistors”, Artech House, inc. Boston, 2002. • Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.
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