Lecture 23 Design for Testability (DFT): Full-Scan (chapter 14) n n Definition Ad-hoc methods Scan design § Design rules § Scan register § Scan flip-flops § Scan test sequences § Overheads § Scan design system Summary Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 1
Definition n Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: § Ad-hoc methods § Structured methods: § Scan § Partial Scan § Built-in self-test (BIST) § Boundary scan DFT method for mixed-signal circuits: § Analog test bus Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 2
Ad-Hoc DFT Methods n Good design practices learnt through experience are used as guidelines: § § § n n Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. Consider ATE requirements (tristates, etc. ) Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods: § § § Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 3
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Observation Point Insertion Control Point Insertion TM=0 TM=1 Copyright 2001, Agrawal & Bushnell Normal operation CONTROL OPERATION VLSI Test: Lecture 23 5
Scan Design § Circuit is designed using pre-specified design rules. § Test structure (hardware) is added to the verified design: § § § Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. § Use combinational ATPG to obtain tests for all testable faults in the combinational logic. § Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 6
Scan Design Rules n n Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. n All clocks must be controlled from PIs. n Clocks must not feed data inputs of flip-flops. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 7
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Correcing a Rule Violation n All clocks must be controlled from PIs. Q* = DC + C Q Comb. logic D 1 Q Comb. logic FF D 2 CK Q* = D 1 D 2 Ck + (D 2 Ck )’Q = D 1 D 2 Ck + D 2’Q +Ck’Q Comb. logic D 1 D 2 Copyright 2001, Agrawal & Bushnell CK VLSI Test: Lecture 23 Q FF Comb. logic 9
Fixing BUS Conection Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 10
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Scan Flip-Flop (SFF) Master latch D Slave latch TC Q Logic overhead MUX SD Q CK D flip-flop CK TC Master open Slave open Normal mode, D selected Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 t Scan mode, SD selected t 14
Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF) Master latch Slave latch D Q MCK Q D flip-flop MCK Logic TCK overhead TCK SCK MCK t TCK SCK Copyright 2001, Agrawal & Bushnell Scan mode SD Normal mode SCK tt VLSI Test: Lecture 23 15
Adding Scan Structure PI PO Combinational SFF logic SFF SCANOUT SFF TC or TCK SCANIN Copyright 2001, Agrawal & Bushnell Not shown: CK or MCK/SCK feed all SFFs. VLSI Test: Lecture 23 16
Comb. Test Vectors PI I 1 I 2 O 2 Combinational SCANIN TC Present state O 1 SCANOUT logic S 1 N 1 S 2 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 PO N 2 Next state 17
Comb. Test Vectors SCANIN I 2 I 1 PI S 1 Don’t care or random bits S 2 TC 0 0 0 0 1 0 0 0 0 PO O 2 O 1 SCANOUT N 1 Sequence length = (nsff + 1) ncomb + nsff + 4 + nsff = (ncomb + 2) nsff + ncomb + 4 N 2 clock periods clock perod ncomb = number of combinational vectors nsff = number of scan flip-flops Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 18
Testing Scan Register n n n Scan register must be tested prior to application of scan test sequences. A shift sequence 0011. . . of length nsff+4 in scan mode (TC=0) produces 0 0, 0 1, 1 1 and 1 0 transitions in all flip-flops and observes the result at SCANOUToutput. Total scan test length: (ncomb + 2) nsff + 4 + ncomb clock periods. Example: 2, 000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks. Multiple scan registers reduce test length. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 19
ATPG Program produces 12 Test vectors for Combinational part with 4 inputs C, R, P 1, P 2 circuit with scan, design and test and Three outputs , Z, Q 1, Q 2 A modulo-3 generation ( Exm. 14. 1) Non –Scan circuit [ 72] has 42 Faults ; 34 test vectors detect 36 out of 42 Faults Scan Circuit : test sequence = (12+2)2+4+12 =44 Fault simulation shows: all faults are detected including 6 undetectable faults in original circuit and Those in multiplexers Normal INPUTS R and C OUTPUT R =1 Q 1 Q 2 = 00 C=1 , R=0 00 01 10 00 Z 0 0 1 0 C=R=0 Q 1+ = Q 1 , Q 2+ =Q 2 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 20
Multiple Scan Registers n n n Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. Test sequence length is determined by the longest scan shift register. Just one test control (TC) pin is essential. PI/SCANIN Combinational logic SFF M U X PO/ SCANOUT SFF TC CK Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 21
Scan Overheads n n n IO pins: One pin necessary. Area overhead: § Gate overhead = [4 nsff/(ng)] x 100%, where ng = comb. gates; nff = flip-flops; Example – ng = 100 k gates, nff = 2 k flip-flops, overhead = 8%. § More accurate estimate must consider scan wiring and layout area. Performance overhead: § Multiplexer delay added in combinational path; approx. two gate-delays. § Flip-flop output loading due to one additional fan-out; approx. 5 -6%. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 22
Hierarchical Scan n n Scan flip-flops are chained within subnetworks before chaining subnetworks. Advantages: § § n Scanin Automatic scan insertion in netlist Circuit hierarchy preserved – helps in debugging and design changes Disadvantage: Non-optimum chip layout. SFF 4 SFF 1 Scanout Scanin SFF 2 SFF 3 Hierarchical netlist Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 SFF 1 SFF 3 Scanout SFF 4 SFF 2 Flat layout 23
Optimum Scan Layout X’ X SFF cell IO pad SCANIN Flipflop cell Y Y’ TC Routing channels Interconnects SCAN OUT Active areas: XY and X’Y’ Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 24
Scan Area Overhead Linear dimensions of active area: X = (C + S) / r X’ = (C + S + a. S) / r Y’ = Y + ry = Y + Y(1 --b) / T Area overhead X’Y’--XY = ------- x 100% XY 1 --b = [(1+as)(1+ -------) – 1] x 100% T 1 --b = (as + ------T y = track dimension, wire width+separation C = total comb. cell width S = total non-scan FF cell width s = fractional FF cell area = S/(C+S) a = SFF cell width fractional increase r = number of cell rows or routing channels b = routing fraction in active area T = cell height in track dimension y ) x 100% Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 25
Example: Scan Layout n n n n 2, 000 -gate CMOS chip Fractional area under flip-flop cells, s = 0. 478 Scan flip-flop (SFF) cell width increase, a = 0. 25 Routing area fraction, b = 0. 471 Cell height in routing tracks, T = 10 Calculated overhead = 17. 24% Actual measured data: Scan implementation Area overhead Normalized clock rate ___________________________________ None 0. 0 1. 00 Hierarchical 16. 93% 0. 87 Optimum layout 11. 90% 0. 91 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 26
ATPG Example: S 5378 Original Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II, 200 MHz processor Number of ATPG vectors Scan sequence length Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 2, 781 179 0 0. 0% 4, 603 35/49 70. 0% 70. 9% 5, 533 s 414 Full-scan 2, 781 0 179 15. 66% 4, 603 214/228 99. 1% 100. 0% 5 s 585 105, 662 27
Automated Scan Design Rule violations Behavior, RTL, and logic Design and verification Scan design rule audits Gate-level netlist Combinational ATPG Scan hardware insertion Scan netlist Combinational vectors Scan sequence and test program generation Test program Copyright 2001, Agrawal & Bushnell Scan chain order Design and test data for manufacturing VLSI Test: Lecture 23 Chip layout: Scanchain optimization, timing verification Mask data 28
Timing and Power n n Small delays in scan path and clock skew can cause race condition. Large delays in scan path require slower scan clock. Dynamic multiplexers: Skew between Ck and TC signals can cause momentary shorting of D and SD inputs. Random signal activity in combinational circuit during scan cause excessive power dissipation. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 29
Summary n Scan is the most popular DFT technique: § § § n Advantages: § § n Rule-based design Automated DFT hardware insertion Combinational ATPG Design automation High fault coverage; helpful in diagnosis Hierarchical – scan-testable modules are easily combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overheads Disadvantages: § § Large test data volume and long test time Basically a slow speed (DC) test Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 30
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