Lecture 11 Input Output Systems CS 311 -Computer

Lecture 11 Input Output Systems CS 311 -Computer Organization Input Output Systems 1

Lecture 11: Input/Output System In this lecture, we will study – – – – Differences between I/O devices and memory Basic I/O and I/O system with I/O controller Bus Protocol Bus arbitration I/O Interface I/O Controller » DMA, Channel – I/O System » » » Memory mapped I/O CPU controlled I/O DMA controlled I/O Channel controlled I/O Processor CS 311 -Computer Organization Input Output Systems 2

I/O Device and Memory • • • Input: Memory <= Input Device Output: Output Device => Memory Difference between I/O device and memory – Operating Speed » In general, speed of I/O devices is slow than memory – Unit of information » Memory: Word » I/O Device: Byte – Autonomy » Memory is synchronized to CPU clock » I/O devices usually operate asynchronously since they are inherently slow and distance apart from memory(sending CPU clock is expensive) – Error rate » Error rate of I/O Device is much higher than memory CS 311 -Computer Organization Input Output Systems 3

Input Output Control • I/O device controller – Controls the functions of I/O device – Sometimes it is integrated into the I/O device – e. g. Disk Controller » Moves head to the desired location on the disk surface » Activates the head to read/write access » Sometimes one controller controls many disk drives • I/O controller – Controls the data moves during I/O » Notify an I/O device to initiate the operation and notify the completion of I/O operation to CPU » Establish a connection between memory and an I/O device for data move » Checking the status of I/O operation » Access memory – e. g. CPU, DMA controller, Channel controller, I/O processor, Front end processor CS 311 -Computer Organization Input Output Systems 4

Basic I/O System Function of I/O Control is included in CPU Memory I/0 Device I/O Dev Controller Interface Memory Bus I/0 Device I/O Dev Controller . . . Interface CPU I/O Controller CS 311 -Computer Organization I/O Bus Input Output Systems 5

I/O System with I/O Controller I/O Dev Controller Interface Memory I/O Dev Interface I/O Controller Memory Bus I/O Dev I/O Bus I/O Controller Interface CS 311 -Computer Organization Interface I/O Dev Controller I/O Dev CPU Interface I/O Dev Input Output Systems I/O Dev 6

Bus Device . . . Device Bus Device – Master Device » Acquires the right to use the bus » Performs control operation for actual data transmission – Slave Device » Perform data transmit operation required by the master device – In an instance when a data transmission takes place, one device is the master, and another is the slave. But the roles of device may change. – Some device can be a master in one instance and a slave in other instance CS 311 -Computer Organization Input Output Systems 7

Bus Components • Data Bus • Address Bus • Control Bus – Master sends Control signals and receives status signals Master Slave In an economical system, One bus can be multiplexed to send Data and Address Control Bus Address Bus Data Bus CS 311 -Computer Organization Input Output Systems 8

Input Output Bus Memory-I/O Common Bus Independent I/O Bus CPU Memory Bus Memory I/O Dev CPU Memory-I/O Common Bus . . . I/O Dev Memory I/O Dev I/O Bus CS 311 -Computer Organization Input Output Systems 9

Protocol Communication between devices with widely different characteristics require a communication rule called Protocol – Synchronous Protocol – Asynchronous protocol CS 311 -Computer Organization Input Output Systems 10

Synchronous Protocol – Master and Slave devices operate in a synchronized fashion – Information(bit, character, block) is synchronized with the clock pulse – Two different methods » Master sends the clock pulse to the slave with the information > Suitable for short distance » Master and Slave both have the synchronized clock pulse generators which are periodically synchronized > Suitable for long distance communications Start Reading Read Complete Clock Pulse Address Data R/W WAIT CS 311 -Computer Organization Input Output Systems 11

Asynchronous Protocol: Serial Transmission Asynchronous Serial Transmission Protocol 0 1 No transmission Start Bit 0 1 1 1 0 0 1 Data Bits 1 1. . . More than 1 Stop Bits – Master and Slave devices must know » Number of bits in a unit of information(byte) » Transmission rate: bit/sec(Baud rate) CS 311 -Computer Organization Input Output Systems 12

Asynchronous Protocol: Parallel Transmission - Handshaking Protocol Asynchronous Parallel Write Transmission Request Acknowledge 1 Address 2 Data Address Next Address Data R/W 3 Req Next Data W Next R/W 4 5 Ack CS 311 -Computer Organization Input Output Systems 13

Asynchronous Protocol: Parallel Transmission - Handshaking Protocol Asynchronous Parallel Read Transmission 1 Address Data 4 R/W 2 Req Next Address 3 5 Ack CS 311 -Computer Organization Data Next Data R Next R/W Input Output Systems 14

Bus Arbiter Bus Arbitration • • In one instance, allow only one master to use the bus Provides the fairness of the bus use amongst the devices – e. g. priority • 3 bus signals – Bus Request(BR): bus master sends BR to get the right to use the bus – Bus Grant(BG): bus arbiter sends BG to requesting bus master as an authorization of the right to use the bus » A requestor amongst other requestors based on the established fairness rule(e. g. , priority) – Busy(BB): the requestor who has the right to use the bus sends BB to notify that bus is in use • 3 different bus arbiter structures – Centralized Parallel Arbitration – Serial Arbitration or Daisy Chain arbitration – Polling Arbitration CS 311 -Computer Organization Input Output Systems 15

Centralized Parallel Arbitration Bus Arbiter (Arbitration Algorithm) BR BB BG Device 0 Device 1 BR BB BG . . . Device n-1 Data Bus CS 311 -Computer Organization Input Output Systems 16

Daisy Chain Arbitration Bus Priority(Arbitration Algorithm) BG Device 0 BGi BGo Device 1 BGi BGo . . . Device n BGi BGo Bus Arbiter BR BB Data Bus • Low priority device may have a danger of starvation • Serial with daisy chain: when there is a failure in the device in the middle of the chain, or broken connection between BGi and BGo, the devices beyond the failing device cannot use the bus CS 311 -Computer Organization Input Output Systems 17

Polling Arbitration Bus Arbiter Device 0 Device 1 . . . Device n BR BB Polling Count Order is the Priority order Data Bus When a bus requesting device gets its device number through polling count, it send BB to arbiter and use the bus. Bus granting time may be too long. CS 311 -Computer Organization Input Output Systems 18

Input Output Interface Function of the I/O Interface • Recognizing address(device address or device code sent by I/O instruction) • Resolving the characteristic differences between I/O devices and Memory(CPU, I/O Controller) – Speed – Unit of information – Autonomy » Highly functional I/O controllers » DMA, Channel, IOP, FEP – Error rate CS 311 -Computer Organization Input Output Systems 19

I/O Interface: Recognizing Device Code • Since there are many I/O devices, a unique device code is assigned to each device. It is received by the interface via address bus. • In each interface, there is a device code decoder Address Bus 1 0 1 DEV SEL 1 Device 101101 Interface CS 311 -Computer Organization 0 Device 111111 Interface Input Output Systems 20

I/O Interface: Resolving Speed Difference • • Data Buffer and its associated flag Receiving data from a slower device - Input – Faster device cannot take away data in its own speed, it must wait until data is ready to be taken away – When can it take away? – When the slower device puts the data in the Data Buffer, Input it sets the Flag. Device – Data can be taken away from the data buffer when the Flag is set and reset after the data is taken away for the next data input • Input Data Buffer Flag Sending data to a slower device - Output – Faster device cannot send data in its own speed, it must wait until data is taken by the slower device – Flag is set by the output device after the data in the Data Buffer is output so that the next data to be output can be stored in the Data Buffer – New data can be stored in the Data Buffer only when the Flag is set CS 311 -Computer Organization Input Output Systems Output Data Buffer Output Device Flag 21

I/O Interface: Resolving Information Unit Difference • • Bit <=> Byte Data Buffer – Input Data Buffer » Serial-in Parallel-out – Output Data Buffer » Parallel-in Serial-out Input to Memory(or CPU) in parallel Input Dev Clock Output Dev Bit Counter Set when 7 Output from Memory(or CPU) Flag CS 311 -Computer Organization Input Output Systems 22

I/O Interface: Resolving High Error Rate • Parity bit – Even parity(even number of 1’s in data bits + parity bit) 1011101 0011011 1 0 – Odd parity(odd number of 1’s in data bits + parity bit) 1011101 0011011 0 1 • Echo Back • Retry and Timeout • EDC/ECC CS 311 -Computer Organization Input Output Systems 23

Parity Generator/Checker b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 Odd Parity Error Odd Parity Even Parity Error Even Parity bit generator CS 311 -Computer Organization Input Output Systems Parity checker 24

Input Output Controller • Functions of I/O Controller – Establishing a connection between I/O Controller and Memory – Storing Memory Address, Direction of data transmission, and Data for memory access – Memory access – Establishing connection between I/O Interface and I/O Controller – Data exchange with I/O device – Notify CPU of completion of I/O operation CS 311 -Computer Organization Input Output Systems 25

DMAC as an I/O Controller A DMA input/output transfers a block, a contiguous words, of data(block) CPU MCR MCG INT R/W ADR DATA DMAR DMAG DMAC data . . . Memory Bus I/O Dev Control Bus Addr Data Bus Memory CS 311 -Computer Organization I/O Bus MCR: Memory Cycle Request MCG: Memory Cycle Grant DMAR: DMA Request DMAG: DMA Grant Input Output Systems CPU initialize DMAC I/O Device Address Function(R/W) Memory Starting Address Number of words I/O Dev to M connection for Cycle Steal by I/O Dev sends DMAR to DMAC sends MCR to CPU sends MCG to DMAC send DMAG to I/O Dev DMAC send Addr and Func to M 26

DMAC: Cycle Steal • CPU is continuously accessing memory, i. e. , using memory cycles during program execution • When a MCR is received, CPU gives the next memory cycle to DMAC so that the requesting I/O Device can use the memory cycle without significant delay that may cause lost data DMAR CPU M Cycle FET EXE FET DMAR EXE FET EXE FET . . . Interrupt FET … Interrupt Routine DMAC CS 311 -Computer Organization Input Output Systems DMAC 27

DMAC: Data Buffer Logic I/O Data Bus(8) Input SL 8 Data Buffer(32) 8 Clock Output Interface Memory LDB/RDB SR 8 Byte Counter =3 I/O Data(32) Reset Memory Bus Data Buffer Logic F LDB/RDB LDB for output RDB for input Resets Byte Counter Data Buffer Full when 4 B Byte Counter = 3 SL for input from I/O bus SR for output to I/O bus Control Logic R/W MCR MCG CPU CS 311 -Computer Organization Memory Data Bus(32) Memory Control Bus Input Output Systems 28

DMAC: Address Buffer and Byte Counter Logic Memory Address Buffer Logic +1 RDB to move Data Buffer to M, or LDB to move M to Data Buffer =0 Word Counter Logic -1 INT Control Logic Receiving MCG form CPU, either LDB/RDB MCG When a word in the block is done for input/output, Increment the address Decrement the word counter When WC = 0 Implies Completion of I/O Request Interrupt CPU CS 311 -Computer Organization Input Output Systems 29

Channel Controller A channel Input/Output command transfers multiple blocks of data Fixed Channel CPU Variable Channel I/O Channel Memory I/O I/O DC Memory I/O CS 311 -Computer Organization Channel CPU I/O Input Output Systems Channel I/O 30

Selector and Multiplexer Channel • • Selector Channel – A channel dedicated to an I/O device usually for a high speed device Multiplexer Channel – A channel is time shared by several sub-channels, where a sub-channel serves for a slow I/O device. Thus a multiplexer channel serves several slow devices in the time multiplexed fashion Sub-channel I/O Multiplexer Channel CS 311 -Computer Organization Input Output Systems 31

Memory Mapped I/O Address Space Input/Output Instruction No particular I/O instruction Use Load/Store instructions When 9

CPU Controlled I/O: Programmed I/O - Input Most elementary I/O – using B(busy) and D(done) flags [1] If B=1, Repeat [1]; [2] B 1; [3] If D=0, Repeat [3]; [4] R Input Data Buffer, D 0; [5] If there is more input data goto [3]; [6] B 0, end; Loop 1: Loop 2: SBZ X JMP Loop 1 START X SDO X JMP Loop 2 IN R, X (M R) (n n-1) (if n>0, JMP Loop 2) STOP X CS 311 -Computer Organization y B 1 n D=1? /Skip if B=0 /B 1 /Skip if D=1 y R n Wasting a lot of cycles here, depending on the speed of input device /B n B=0? Buf, D 0 End? y B 0 0 Input Output Systems 33

CPU Controlled I/O: Programmed I/O - Output Most elementary I/O – using B(busy) and D(done) flags [1] If B=1, Repeat [1]; [2] B 1; [3] If D=0, Repeat [3]; [4] Output Data Buffer R, D 0; [5] If there is more input data goto [3]; [6] B 0, end; Loop 1: Loop 2: SBZ X JMP Loop 1 START X SDO X JMP Loop 2 OUT R, X (R M) (n n-1) (if n>0, JMP Loop 2) STOP X CS 311 -Computer Organization y B 1 n D=1? /Skip if B=0 /B 1 /Skip if D=1 y Buf n Wasting a lot of cycles here, depending on the speed of input device /B n B=0? R, D 0 End? y B 0 0 Input Output Systems 34

CPU Controlled I/O: Programmed I/O • • Inefficient because CPU wastes a lot of cycles simply waiting for the slow I/O device to respond Example Speed of CPU = 100 MIPS: Assume that identical instruction execution time Input 1, 000 characters from a keyboard, 1 character input time is 1 sec. How many times SDO instruction in Loop 2 will be executed per character input ? 100 MIPS implies that execution time of an instruction is 10 -8 sec. To simplify the problem, neglect the first three instructions and the last instruction since they are executed only once at the beginning and at the very last. Let X be the number of executions of SDO instruction in Loop 2. Number of instruction executions for one character input becomes; X + (X-1) + 4 Thus, (2 X + 3) x 10 -8 sec = 1 sec Therefore, X = 5 x 107 , i. e. , it will be executed 50 million times CS 311 -Computer Organization Input Output Systems 35

CPU Controlled I/O: Interrupt Processed I/O Interrupt processed I/O allows to utilize the slow I/O device’s response time for the productive work, if there is any Loop 1: Loop 2: SBZ X JMP Loop 1 START X SDO X JMP Loop 2 IN R, X (M R) (n n-1) (if n>0, JMP Loop 2) STOP X Waste of CPU cycles in programmed I/O By allowing Device X to interrupt CPU when data buffer is ready, this much CPU cycles can be utilized for the productive work. Loop 1: SBZ JMP START Loop 3: ION ( Execute other tasks …………. . Interrupt from X CS 311 -Computer Organization Done in the interrupt processing routine Input Output Systems X Loop 1 X X ) IN R, X (M R) (n n-1) (if n>0, JMP Loop 3) STOP X 36

DMAC Controlled I/O • CPU must send DMAC with – – – Direction of data transfer, i. e. , Function(R or W) Starting address of the block Word count (Address of DMAC), I/O device address (Data block address in I/O device) • Instruction – Output instruction if programmed I/O system is used – ST instruction if memory mapped I/O system is used CS 311 -Computer Organization Input Output Systems 37

Channel I/O • Channel Program stored in memory – Channel program consists of a linked list of Channel Command Words(CCW) CCWn CCW 2 CCW 1 CCW 0 . . . CAW • Instruction – START Cn, Dn • CAW • CCW – Information provided to DMAC about data block and direction of transfer CS 311 -Computer Organization Input Output Systems 38

Input Output Processor Input/Output Processor – Handling of Data to be input/output – Editing, Debugging, Validating, … – 2 kinds of I/O Processors(computers) » Off-line I/O computers » On-line I/O computers Off-line Main Computer Mag Tape Dedicated I/O Computer Mag Tape Printer CPU Memory Disk CS 311 -Computer Organization On-line Memory Disk Input Output Systems Graphics Dev Computer 39

On-line I/O Computers I/O Computer Main Computer Printer CPU Memory Disk Graphics Dev Computer I/O Computer Main Computer Printer CPU Memory CS 311 -Computer Organization CPU Memory Input Output Systems Graphics Dev Computer 40