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Lab Seminar Formal Verification of UML model and requirement March 28 th 2005 KIM, Lab Seminar Formal Verification of UML model and requirement March 28 th 2005 KIM, YUN GOO

Shin Ko Ri, Shin Wol Sung 1, 2 RMS § Samchang won the bid Shin Ko Ri, Shin Wol Sung 1, 2 RMS § Samchang won the bid of SKR 1&2, SWS 1&2 RMS last January § About, 10, 000, 000 won (100억) § Delivery date is 2008~2010 § Development of S/W for RMS computer will start in this year § Quality class ; § Q for some 1 E monitor § T for RMS computer § V&V activities are required 2

Research Project of mocie (commerce industry and energy) § Title : Development of V&V Research Project of mocie (commerce industry and energy) § Title : Development of V&V System for NPP Safety Critical S/W in Object Oriented Development Environment (객체 지향 개발 환경에서의 원전 안전성 소프트웨어를 위한 V&V 시스템 개발) § Period : 2005. 3 ~ 2007. 2 § Fund : 340, 000 won § Research on commission(위탁) : § Korea Univ. Theory and Formal Method Lab. § Prof. Choi, jin young 3

Content of Research Project. § Application of Object oriented development to NPP safety critical Content of Research Project. § Application of Object oriented development to NPP safety critical S/W (as background research) § Development of S/W V&V with UML in OO environment § Use UML in each S/W life cycle. § Auto code generation from modeling. § Linked UML for traceability § Formal verification from UML § Conversion UML Specification model and specification to Formal § Test case generation in UML specification and Formal spec. § Application of developed V&V method to RMS computer S/W 4

S/W V&V with UML RMS Sample Module Code Generation Software Test Apply to RMS S/W V&V with UML RMS Sample Module Code Generation Software Test Apply to RMS S/W V&V SRS for RMS SDD for RMS Execution Test CD SRS SDD Statement Automatic UML UML Code Generation Concept Requirements Design Conversion algorithm to Formal specification Formal verification Procedure Implementation Test case Generation Test Case Generation-II STATEMATE MAGNUM Test Case Generation-I 2 nd year 1 st year 5 : Korea Univ.

Conversion UML to Formal specification § Development of verification system of UML with formal Conversion UML to Formal specification § Development of verification system of UML with formal method. § Conversion algorithm from UML to Formal spec. § Consistency of UML model and Formal spec. § Verification characteristics required in NPP S/W § Verification characteristics from System. Convert to UML (Rhapsody) Formal spec Statemate MAGNUM 6 Formal Verification TEST case Generation

The Omega project § Supported by IST (Information Society Technologies, European research project) § The Omega project § Supported by IST (Information Society Technologies, European research project) § Title : UML based modeling of real-time and embedded systems with formal validation(20022005) § Project Acronym: OMEGA § Project Reference: IST-2001 -33522 § Start Date: 2002 -01 -01 § Duration: 36 months § Project Cost: 4. 30 million euro 7

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The UVE tool (UML Verification Environment) § I. Schinz, T. Toben, Ch. Mrugalla, B. The UVE tool (UML Verification Environment) § I. Schinz, T. Toben, Ch. Mrugalla, B. Westphal, § The Rhapsody UML Verification Environment § In Proceedings of the 2 nd International Conference on Software Engineering and Formal Methods (SEFM 2004), IEEE September 2004 § Rhapsody is a UML tool from I-logix. § Rose ; IBM rational § Together ; Boland 9

Main idea of paper Modeling Requirement § Modeling : § UML, Rhapsody C++ § Main idea of paper Modeling Requirement § Modeling : § UML, Rhapsody C++ § Export XMI(XML Metadata Interchange) files § SMI (System Modeling Interface, developed by OFFIIS) § FSM (Finite state machine) § Requirement ; § Pattern definition § LSC (Life Sequence Charts, from Massage Sequence Charts and Sequence Diagram) § CTL (Computation tree logic) § VIS (Verification Interacting with Synthesis) Model checker Output trace is back translated into UML STD (Symbolic timing diagram) § § 10

Example of Verification Procedure (1) § An Informal requirement ; E 1 Vending Machine Example of Verification Procedure (1) § An Informal requirement ; E 1 Vending Machine C 50 Water ; 50 cent Soft ; 1 Euro Tea ; 1 Euro 50 cent § Whenever a customer wants to buy a water drink (thus, inserts at least one 50 cent coin followed by pushing the water button) and the Vending Machine is not out of water drinks, then a water is prepared and dispensed to the customer 11

Example of Verification Procedure (2) § Class Diagram UML LSC VIS STD LSC 12 Example of Verification Procedure (2) § Class Diagram UML LSC VIS STD LSC 12

Example of Verification Procedure (3) § The state chart of the Coin. Validator ; Example of Verification Procedure (3) § The state chart of the Coin. Validator ; FSM LSC VIS STD LSC 13

Example of Verification Procedure (4) § Requirement as LSC (Life Sequence Charts) UML LSC Example of Verification Procedure (4) § Requirement as LSC (Life Sequence Charts) UML LSC VIS STD LSC 14

Example of Verification Procedure (5) § VIS Model checking and produce automatically errorpath UML Example of Verification Procedure (5) § VIS Model checking and produce automatically errorpath UML LSC VIS STD LSC 15

Example of Verification Procedure (6) § VIS also generate STD (Symbolic timing diagram) UML Example of Verification Procedure (6) § VIS also generate STD (Symbolic timing diagram) UML LSC §After fillup, VM does not dispense water VIS STD LSC 16

Summary § RMS S/W V&V should be started in this year. § Research project Summary § RMS S/W V&V should be started in this year. § Research project from mocie § UML V&V method § Formal verification § Conversion algorithm should be developed. § Research from OMEGA § UML verification environment § Rhapsody, LSC, FSM, STD § Further work § Detail development of V&V for UML (Research project) § Real S/W V&V plan should be prepared for RMS S/W 17