IPCHINOOK An Integrated IPbased Design Framework for Distributed

IPCHINOOK: An Integrated IPbased Design Framework for Distributed Embedded Systems Written by Pai Chou, Ross Ortega, Ken Hines, Kurt Partridge, and Gaetano Borriello Presented by Frank Gennari

Overview of IPCHINOOK is a distributed embedded system design, synthesis, and simulation tool. Ø Ø Ø Ø Component-based design Stresses reuse of software modules Synthesizes communication and synchronization instructions Co-simulation engine for rapid evaluation Integrated user interface High-level abstractions of hardware and software Automated generation of error-prone details

Problems Addressed by IPCHINOOK Ø IP Composition Problem: Limitations of fixed APIs, time consuming custom integration code, duplicated component state Solution: ip. Chinook uses a separate component assembly step leading to reusable composition constructs Ø Communication Synthesis Problem: Custom intermodule communication software must be written based on system architecture Solution: Automating this process quickly leads to a more portable solution Ø Rapid Evaluation Problem: Fast co-simulation is needed at different levels of the design process and profiling is required for feedback to the designer Solution: Selective focus provides more details for parts of the simulation

Overview of IPCHINOOK Design Framework System Functionality Available Devices, Hardware Topology

Modal Processes Consist of … Ø Ports provide logical communication contact points for Ø Ø interprocess communication Channels connect an output port to one or more input ports Events are arrivals of messages that trigger a handler Handlers send messages and return mode changes in steps • Can send messages to output ports with one step delay due to input buffering Modes specify a mapping from ports to handlers • They can be independently active or inactive

Active Mode Change Process 1. Vote Collection: Each handler returns a set of votes on activating/deactivating modes 2. Vote Reconciliation: Votes and ACTs are examined to determine what mode changes should be made • Conflicts are resolved by vote priority 3. Vote Distribution: New set of active and inactive modes are distributed to affected modal processes

Abstract Control Types (ACTs) ACTs are high-level primitives that coordinate, adapt, and define protocols and modify votes to maintain mode relationships ip. Chinook supports a library of reusable ACTs as well as user-defined ACTs The seq. Loop ACT controls the mode of the stopwatch, an Esterel example

Esterel Wristwatch Example W Update Watch Z Watch. UI R L Stopwatch A Alarm Shown Reg Set E C Zero Run Shown seq. Loop WS SS AS Lap Stopwatch. UI Enb Chime ACTs Shown Reg Set Modal Processes Alarm. UI UI-independent composition UI-specific composition

Target Description Target description … Ø Defines a target architecture • Processors (microprocessor or FPGA) • Operating System • Communication Protocols (I 2 C, CAN, SCSI, USB, Ir. DA, Ethernet) Ø Defines the allocation function that maps modal processes and channels to the architecture • Processes Processors (running multiple processes) • Logical comm channels architectural comm links

Mode Manager Synthesis Ø A mode manager is the part of the run-time system that manages control communications according to the ACTs Ø Mode managers handle system state maintenance Ø A mode manager for each processor is automatically synthesized for heterogeneous distributed systems • Tradeoff of space, performance, and determinism • Mode, event, comm. , and dataflow synchrony models Ø A centralized mode manager is synthesized for simulation • Single processor mode synchrony

Communication and Interface Synthesis Communication synthesis Ø Abstract communication protocols implemented on the target architecture allow modal processes to exchange messages Interface Synthesis Ø Generates interfacing logic and low-level device drivers to connect processing elements together Abstract communication protocols implemented with busses Ø Output port annotated with blocking style and deadline constraints Ø Input port annotated with queuing info (size and overflow behavior) Target independent target dependent System architects can investigate tradeoffs, explore design space

Generated Communication Structure Producer Process Designer Abstraction Out. Port Consumer Process In. Port Message Router Device Driver Comm. Chip Device Driver Generated Infrastructure Comm. Chip

Communication Synthesis Steps 1. Multi-hop deadline distribution Ø Automatically creates hop processes to route a message through intermediate processors and busses Ø Deadline is distributed along entire path 2. Bus protocol attribute synthesis Ø Protocol determined based on parameters of all messages Ø Message Ids, processor Ids, priorities, and queues Ø Synthesized with routing information for RTOS 3. Message router generation 4. Device driver instantiation Ø Ø Device drivers abstract the designer from the protocol Instantiated from a protocol library Read and write to physical processor pins Glue logic for I/O ports or memory mapped IO

HW/SW Co-Simulation - Pia Ø Designers can execute a model at any synthesis stage Ø Selective focus • Highest level of abstraction = fastest simulation speed • Designers can view low-level details of regions of interest • Can dynamically zoom in and out of simulation regions Ø Support for high-level debugging • Modal processes and ACTs • Step through mode traces and event traces

Selective Focus Pia keeps track of several versions of interface entry calls and selects the best version (runlevel) based on level of detail Ø Coordinate runlevels between communicating interfaces Ø Must not leave residual state behind Ø Runlevel must be indistinguishable to the applications and interfaces that use it Ø Communications are tagged with runlevel to solve these problems Example: Wubble. U Ø Small PDA with wireless connection

Ir. DA Protocol Stack

Hardware Simulation Real hardware can also be simulated Ø Simulator nodes can be distributed across the internet Ø Vendors can put parts on the web and allow designers to test them remotely Ø Designers can avoid building a hardware prototype Ø IP providers can limit access to their products Ø Can exploit parallel simulation with remote hosts

Conclusions ØIPCHINOOK is a comprehensive HW/SW cosynthesis framework for distributed embedded systems. ØDesign space exploration is enabled through mapping a high-level design onto various target architectures ØDesign reuse and retargetability are important aspects to system design ØSimulation allows validation of design at different synthesis stages ØSelective focus results in an efficient yet detailed simulation Ø Handlers and tools were written in Java

Future Work 1. Allow verification of mode liveliness and safety properties 2. Expand debugging to directly use coordination information 3. Expand the mode manager framework to include hardware IP 4. Broaden the communication synthesis to support networked distributed embedded systems