Introduction to Xilinx CPLDs Agenda

Introduction to Xilinx CPLDs

Agenda • • • 2 CPLD Introduction XC 9500 Family Overview Cool. Runner XPLA 3 Overview Cool. Runner-II Overview IQ Products for Automotive and Industrial • Software Updates and Online Support • Customer Success Stories

Complex Programmable Logic Device macrocells interconnect macrocells A hybrid of PLD blocks & interconnect for mid-size logic designs 3

Specification CPLD Design Flow libraries HDL Schematic Capture Synthesis netlist CPLD Design Flow Verification Gates of the design. . . Simulation 0100 1110 1100 1111 test vectors Implementation Translate Fitting Timing Analyzer Back-Annotation Download/ Program System Debug printed circuitboard 4 device . . . are “fitted” to the CPLD

High Performance • Pin-to-Pin combinatorial delay – Time from input, thru interconnect to output (ns) CPLD • Maximum registered frequency – Fastest operation of flip-flops (MHz) CPLD Macrocell TPD (ns) 5 f. MAX (MHz)

Wide Package Offering • High pin count package for lots of I/Os • Maximum logic with minimal I/Os • Logic consolidation for space (vs. discrete devices) A CPLD package • Lower cost packagingsmaller board! means a CPLD 6 CPLD

CPLD Voltage Integration 5 v, 3. 3 v, 2. 5 v, 1. 8 v and 1. 5 v • 3. 3 v & 2. 5 v is the current market trend moving to 1. 8 v and below for portable and low power applications • Cost reduction to eliminate 5 v supply and regulators with 5 v tolerance • Some components will not migrate to 3. 3 v or below • Need to interface with 3. 3 v, 2. 5 V, 1, 8 v and/or 1. 5 v components 5 v* 5 v* CPLD 3. 3/2. 5/1. 8 v 3. 3 v* 5 v* 1. 8 v* 2. 5 v* * 3. 3 v CPLD required to interface with 5 v, 3. 3 v & 2. 5 v components * 2. 5 v CPLD required to interface with 3. 3 v, 2. 5 v & 1. 8 v components *1. 8 v CPLD required to interface with 3. 3 v, 2. 5 v, 1, 8 v & 1. 5 v components 7

System Integration Advantage 8

System Level Savings • High volume economies of scale – Single chip for multiple system solutions • Increase volume means reduction in all related costs • Reference designs – Minimize risk and shorten design cycle • Lowest cost per I/O – Examples include • On The Fly (OTF) reconfiguration – Two devices for the price of one 9

Designers Need Low Power • Longer lasting battery life • Lower overall system cost (eliminate fans/ reduce power supplies) • Increased system reliability • Fits into hand-held applications 10

CPLD Advantage over Discrete Logic High Speed CMOS Logic 74 HC 373 XPLATM Architecture 74 HC 373 74 HC 137 SOL 24 74 HC 137 74 HC 374 TQFP 100 74 HC 137 TSSOP 24 74 HC 157 74 HC 00 74 HC 20 74 HC 21 74 HC 138 SOL 24 74 HC 138 Equivalent to XCR 3128 XL Or XCR 3064 XL 3. 3 V parts in the same package bridging two densities for added design flexibility Real design example: Aircraft Passenger Handset - Smaller PCB with less layers (lower cost) - 7 to 3 layers! - One part to purchase & stock, less inventory - One part to pick and place in manufacture, saving time - Design can be changed and enhanced without PCB re-layout - even in the field - Stock and purchase one part instead of 17 in this example! 11

Units Shipped Xilinx CPLD High Volume Shipments • Xilinx currently ships >10 M CPLD units per Qtr • WW CPLD market share growing at >1% per Qtr 12

CPLD Product Portfolio – – – 1. 8 V Real. Digital – – core 1. 5 V - 3. 3 V I/O SSTL, HSTL, LVCMOS, LVTTL Lower power • Data. GATE Clocking features • Clock Divide • Cool. CLOCK • Dual. EDGE – I/O banking 13 – – 2. 5 V core 1. 8 V - 3. 3 V I/O LVCMOS, LVTTL I/O banking 3. 3 V core 2. 7 V - 5 V I/O LVCMOS, LVTTL Low power • Fast Zero Power – 3. 3 V core – 2. 5 V - 5. 0 V I/O – LVCMOS, LVTTL

Quick Design Capability with CPLDs

Product Lifetime Dynamics Units Cellular Target high volume, short production life applications PDA PC Games TV 1 2 Years in Production New products stay in volume for shorter periods, Time To Market is critical! 15

ASIC Development Take Too Long! • Product life cycles maybe shorter than ASIC development time – Multiple ASIC spins may miss the market window – Smaller than expected run rates may not justify the ASIC development cost • Long ASIC development times do not allow last minute design revision changes – Revisions leave little time to run in 16 production

ASICs Give Designers Only ONE Chance Freeze design here No chance for last minute design changes ASIC Spec System Integration Design & Verification Silicon Prototype Silicon First Production Ship Re-programming allows last minute design changes CPLD Spec l 17 Design & Verification System Integratio n First Ship Freeze design here CPLD flexibility allow performance analysis and late HW/SW changes meeting customer needs and improves Time To Market with faster, lower risk designs

Cool. Runner Reference Designs • Shorten design cycle time – Eliminate code porting costs for next design cycle • Re-use of HDL is reliable and stable • Minimize design risk by using reference designs – Availability of reference designs prepares you for unexpected system changes • Update main processor but it does not incorporate correct bus interface • Further improve customer’s Time To 18

Faster Designs with FREE Cool. Runner Reference Designs Coming soon Free VHDL design code: www. xilinx. com/products/xaw/coolvhdlq. htm 19

Cool. Runner-II Design Kit 20

Development Board & Cable Support Note: There may be regional variations because of different mains voltages - check locally for full part number 21

CPLD Software Improvements in 6. 1 • Ease of use – Improved CPLD process flow • Single process (Implement Design) will pull the design through the entire fitting process • Granular control still possible for power users by expanding individual processes XC 9500 XL / XV Product – New design creation aids • Overview New project wizard leads the user through the project creation process • Add existing source / Create new source processes - assist in getting started faster – Centralized process properties menu • Web Update – File Numberin utility checks for service Built Here 22

Xilinx CPLD Process Leadership Non-Volatile Technology Year used in Memories Year used in SPLD/CPLD Pioneer Bipolar Fuse 1978 MMI (AMD) EPROM 1979 1984 Altera EP-series 5 V EEPROM 1986 1991 Lattice isp. LSI 5 V FLASH 3. 3 V FLASH 2. 5 V FLASH 23 1973 1990 1993 1996 1995 1998 2000 Xilinx XC 9500 XL Xilinx XC 9500 XV

Higher Voltage CPLD Solutions To Fit Every Need • • • 5 / 3. 3 / 2. 5 V core 36 -288 macrocells High Performance Superior pin-locking Low cost XC 9500 Families XC 9500 XV 5 V core 24 XC 9500 XL 3. 3 V core 2. 5 V core

XC 9500/XL/XV Family Features Overview CPLD Designer Needs High Performance Time to Market Fit in Existing Flow Package offering 5 v, 3. 3 v & 2. 5 v Lowest cost 25 • • • High f. MAX = 278 MHz Fast TPD = 3. 5 n. S Instant productivity software tools Best pin-locking capability Best ISP/JTAG support Support for all ATE manufacturers Advanced packaging including CSP XC 9500 XL for 3. 3 v (5 v tolerant & 2. 5 v I/O) XCR 9500 XV for 2. 5 v (1. 8 v & 3. 3 v I/O) Best CPLD pricing in the industry!

XC 9500 XL / XV Families 3. 3 v ISP XC 9536 XL XC 9572 XL XC 95144 XL XC 95288 XL 2. 5 v ISP XC 9536 XV XC 9572 XV XC 95144 XV XC 95288 XV Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 tpdns) XC 9500 XL ( 5 5 5 7. 5 tpdns) XC 9500 XV ( 4 5 5 6 Registers 36 72 144 288 f XC 9500 XL 178 178 125 SYSTEM XC 9500 XV 200 178 151 PC 44 Packages CS 48 VQ 44* VQ 64 TQ 100 TQ 144 CS 144 PQ 208 BG 256 FG 256* CS 280* 26

XC 9500 5 V Family XC 9536 XC 9572 XC 95108 XC 95144 XC 95216 XC 95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 5 7. 5 10 15 36 72 108 144 Max. User I/Os 34 72 108 133 Packages 44 VQ 44 PC 84 PC 100 TQ 100 PQ 160 PQ t. PD (ns) Registers 48 CSP 27 44 PC 84 PC 100 TQ 100 PQ 216 160 PQ 208 HQ 352 BG 288 192 208 HQ 352 BG

XC 9500 5 V Family XC 9536 XC 9572 XC 95108 XC 95144 XC 95216 XC 95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 5 7. 5 10 15 36 72 108 144 216 288 34 72 108 133 166 192 84 PC 100 TQ 100 PQ 160 PQ 208 HQ 352 BG TPD (ns) Registers Max. User I/Os Packages 44 VQ 44 PC 48 CS 28 44 PC 84 PC 100 TQ 100 PQ

XC 9500 XL 3. 3 V Family XC 9536 XL XC 9572 XL XC 95144 XL XC 95288 XL Macrocells 72 144 288 Usable Gates 800 1600 3200 6400 t. PD (ns) 5 5 5 Registers 36 72 144 288 Max. User I/Os Packages 29 36 36 72 117 192 PC 44 VQ 44 CS 48 VQ 64 TQ 100 CS 144 TQ 144 6 TQ 144 PQ 208 BG 256 FG 256 CS 280

XC 9500 XV 2. 5 V Family XC 9536 XV XC 9572 XV XC 95144 XV XC 95288 XV Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 t. PD (ns) 5 5 5 6 Registers 36 72 144 288 Max. User I/Os 36 72 117 192 PC 44 VQ 44 CS 48 TQ 100 Packages 30 TQ 100 CS 144 TQ 144 PQ 208 FG 256 CS 280

XC 9500/XL/XV Family Features Driving the ISP Revolution • Complete support of ISP designer’s Product Life Cycle • Provides industry’s best pin-locking CPLD at lowest price • Complete “state-of-the-art” software support • CPLDs key part of the Xilinx “total logic solution” • Benefits of ISP: – No need for costly device programmers, fewer board re -spins, less scrap and re-work, reduces design and development time scales, enables field upgrades, eliminates unnecessary package handling, CPLD 31 x Program the whole board not each chip!

XC 9500/XL/XV Family Features Most Complete JTAG Testability • IEEE Std 1149. 1 boundary-scan – Testability & advanced system debug/diagnosis – 8 instructions supported (incl. CLAMP) • Full support on all family members • 1532 Industry-standard ISP interface • Complete 3 rd party support • Benefits of JTAG: Improved testability, higher system reliability, cheaper test equipment, shorter test time, reduced spare board inventories, reduces device handling. 32

XC 9500/XL/XV Family Features Innovative CSP Packaging • New 48 -pin Chip Scale Package (CSP) • • • – 1/3 size VQFP-44, 82% smaller than PLCC-44 – Big board space benefits New 144 -pin CSP (117 user I/Os) Uses standard IR surface mounting process Supports industry’s high growth market segments – Communications, Computers, Consumer PC 44 5. 6 X 33

XC 9500/XL/XV Family Features New price points open up new apps • Motherboards for PCs and servers • PC peripherals and add-on cards – DVD players/controller cards – Graphics cards • Automotive – Engine control – Automotive navigation systems (GPS) • Consumer – LAN / DSLAM – Video Games/Toys 34

CPLD Software Improvements in 6. 1 • Ease of use – Improved CPLD process flow • Single process (Implement Design) will pull the design through the entire fitting process • Granular control still possible for power users by expanding individual processes Cool. Runner XPLA 3 Product – New design creation aids • Overview New project wizard leads the user through the project creation process • Add existing source / Create new source processes - assist in getting started faster – Centralized process properties menu • Web Update – File Numberin utility checks for service Built Here 35

XCR 3000 XL Family Features Overview CPLD Designer Needs High Performance Time to Market Package offering Low power 36 • • High f. MAX = 200 MHz Fast TPD = 5 n. S Instant productivity software tools Best ISP/JTAG support • World’s Smallest BGAs (CP 56) • Industry’s 1 st & most efficient architecture - PLA • Ultra low power operation • No power/performance tradeoffs • Low Power = High Reliability THESE PARTS ARE FOR LOW POWER APPLICATIONS!

Cool. Runner XPLA 3 Family 37

XCR 3000 XL Family Features Low Power • Dynamic Battery Life – Populated with 16 bit counters @ 20 MHz – 2 AA batteries – Non Cool. Runner devices in low power mode 200 180 160 140 120 100 80 60 40 20 0 CY 37128 M 4 A 3 M 4 LV 7000 A 3000 A ISPLSI 2128 VE XC 95144 XL XCR 3128 XL Hours of operation 3. 3 V CPLD Low Power Leadership! 38 Competitive Device Families

XCR 3000 XL Family Features Extra ‘Hidden’ Benefits of Low Power • Eliminates Expensive Heat Sinks & Cooling Fans – Heat Sinks: $ 0. 50 - $ 12. 00 – Fans: $ 3. 50 and up • Decreases Power supply component size for: – High Performance – Small Portable Form Factors • Computing Lap & Palm Enclosures • Higher product density Less Heat = Higher Performance, Cost Savings & Reliability! 39

Thermal Emissions Comparison Ambient Xilinx XCR 3256 XL-7 TC 144 Cypress CY 37256 VP 160 -100 AC Lattice M 4 LV-128/64 -10 YC Altera EPM 7256 AETC 144 -7 Altera EPM 3256 ATC 144 -7 25 30 35 40 45 50 55 Degrees Centigrade 60 Lattice isp. LSI 2192 VE-100 LT 128 • Devices programmed with 16 bit counters with the MSB brought out to an LED and operated at 50 MHz • Where applicable, competitive devices were in non-turbo mode • Note the MACH 4 device is 128 macrocells, Lattice is 192 macrocells (largest in the family) 40

Thermal Characteristics Altera 3 K Test IR 00004. ISI The Altera MAX 3000 A 256 macrocell device was powered up in low power mode and loaded with a 16 bit counter and clocked at 50 MHz. A thermal imaging camera measured the Altera device (P 1) to be @ 40. 23ºC, (P 2) was a Cool. Runner XCR 3256 XL device @ 30. 03ºC, the back ground temperature was 22. 88ºC (P 3) 41

Higher System Reliability Infant Mortality Constant Failure FITS Wear out Temperature Time u Activation Energy EA Aggravated by Temperature! u Increased Temperature = Decreased Reliability 42

Lower Power = Smaller Packages • XPLA 3 supports 17. 6 mm 44 PLCC 12 mm 7 mm 12 mm 48 CS 6 mm 43 7 mm 6 mm 56 CP 17. 6 mm 44 VQ small industry standard packages • New Chip Scale Packaging – CS 48 – CP 56

The Real. Digital CPLD A New Class of CPLD with High Performance and Ultra Low Power without Compromise!

CPLD Sense amp Designs Have Migration Limits 0. 60 µ 0. 50 µ 0. 35 µ 0. 25 µ 5. 0 Volt Devices 3. 3 Volt Devices High speed and low power barrier 2. 5 Volt Devices CR-II FZP 1. 8 Volt, 0. 18µ Devices 0. 18 µ Sense amps don’t scale well Sense amp based CPLD technologies don’t scale effectively beyond 0. 18µ 45

High Level Architecture Clock and Control Signals Function Block 1 MC 2 I/O Function Block n 16 FB MC 1 MC 2 16 FB I/O I/O MC 16 16 Fast Inputs AIM PLA 16 40 I/O MC 16 Fast Inputs I/O Blocks 40 I/O 46 PLA 16 16

Function Block Architecture From AIM 40 MC 1 PLA Array 40 x 56 To I/O Block 16 56 Product Terms MC 16 3 Global Set/Reset 47 Feedback to AIM Global Clocks

Logic Allocation Advantage PAL: Requires 4 product terms! C A B Can NOT share common logic X Indicates ‘used’ junction Indicates ‘unused’ junction Indicates ‘fixed’ junction 48 Y PLA: Requires only 3 product terms! A B C X=A&B#C Y = A & B # !C X Y Common logic may be shared in Cool. Runner-II

FB Inputs from AIM 40 Macrocell Architecture application notes: http: //www. xilinx. com/apps/epld. htm PLA Array 49 P terms Macrocell 4 Control Terms from I/O Block (Fast Input) Feedback to AIM PTA PTB PTC PTA CTS GSR GND VCC GND S D/T to I/O Q FIF Latch Dual. EDGE CTC PTC 49 GCK 0 GCK 1 GCK 2 PTC CE CK R PTA CTR GSR GND

I/O Block Characteristics HSTL & SSTL VCCIO to AIM Input Hysteresis to Macrocell (Fast Input) VREF for Local Bank VREF I/O Pin 128 macrocell and larger devices 3. 3 V - 1. 5 V Input Slewrate from Macrocell Enabled Control Term PTB GTS[0: 3] CGND Open Drain Disabled 50 VCCIO Weak Pullup/Bus Hold I/O Pin 4 /

I/O Flexibility XC 2 C 32 XC 2 C 64 XC 2 C 128 XC 2 C 256 XC 2 C 384 XC 2 C 512 I/O Banks 1 1 2 2 4 4 LVTTL 33, LVCMOS 18, 25, 33 & 15*I/O SSTL 3 -1(3. 3 v), SSTL 2 -1 (2. 5 v), HSTL 1 (1. 5 v) Input hysteresis control Slew rate control Cool. CLOCK Data. GATE Clock doubler Clock divider Bus hold output Hot pluggable Note: 1. 5 v inputs need hysteresis 51

Real. Digital Design Advantage Turbo vs Non Turbo Larger R = slower response Vcc & less power A B C Sense amplifier 0. 25 m. A each Standby Higher ICC at Fmax • Traditional CPLDs bipolar sense amp product terms – Always consumes power – Even at standby – Performance is traded for power consumption as devices get larger 52 A B C D Real. Digital: CMOS Everywhere - Zero Static Pow • Cool. Runner-II Real. Digital design uses 100% CMOS for product terms – Virtually no standby current – Combines high performance & ultra low power

Reducing Power • Icc = C x V x f • To reduce power: – Lower capacitance – Lower voltage – Lower frequency ~ 200 m. A Icc 0. 18 m lowers capacitance Low VCC @ 1. 8 V How can we reduce the frequency? st) Volt (e 1. 8 lt 2. 5 Vo 3. 3 Volt Tradition al Sense Amp Designs ~ 100 m. A Note: 128 MC device estimate 53 Frequency ~ 200 MHz

Low Power CPLDs • Cool. Runner XPLA 3 – Low power – 3. 3 V core with 5 V tolerance • Cool. Runner II – – Ultra Low Power Lowest Cost Feature Rich 1. 8 V core with 1. 5 v to 3. 3 V compatibility And our parts still run on GRAPEFRUIT! 54

Beware! Not all ‘Low Power’ Logic is Created Equal! • Some logic devices have ‘power down’ modes – Complicates timing models (non-deterministic) – Power down modes slow timing (TPD / Fmax) when used • Some logic devices ‘shut down’ when not active – Latency periods apply for wakeup (typ. 50 ns) – No power savings when operating • Choose Logic to simplify design process 55 – No speed / power tradeoffs

500 m. V Input Hysteresis • Supports simple oscillation schemes • Ideal for slow edge rate, noisy signals – – V Cool. Runner-II In Analog comparators & sensors Hall effect switches IR inputs R/C oscillators • Eliminate external Schmitt trigger buffers • Reduces power consumption with slow signals 56 _ + Cool. Runner-II

Solving Signal Integrity Challenges • Noisy, slow analog signals – – Hall Sensor R/C Oscillator XTAL input RFI, EMI effects Input hysteresis • With input hysteresis – Analog signals function as digital inputs – Saves power by non-linear operation – Added noise immunity 57

Dual. EDGE: Performance Enhancing • • In all Cool. Runner-II devices Edge detect doubles clock up to 500 MHz Selectable on a per macrocell basis Ideal for Double Data Rate (DDR) memory devices Doubler 58

Clock Divider: Power Efficient • 128, 256, 384 & 512 Divider • • macrocell 2, 4, 6, 8, 10, 12, 14 or 16 digital clock divide Reduce external oscillators 50% duty cycle Reduces cross talk Divide by 4 System Clock Sync Reset Div_clock Phase bit = 0 Div_clock Phase bit = 1 59

Cool. CLOCK • Further power reduction plus performance – Combination of clock divider & Dual. EDGE (clock doubler) – Divide incoming clock by two (lowing total power), then double at macrocell for high speed requirements Global Macrocell Input Divide by 2 Doubler Divider 60 CPLD Original frequency Output

Data. GATE • Another low power enhancement – Control Data. GATE signal externally or internally – User programmable on/off switch for specific inputs • Only enable inputs when necessary • Great for power reduction on wide logic interfaces – Latch data when valid, reduces unnecessary signal toggling Data. GATE Diagram Data. GATE control signal Input pin 61 Gated internal signal

The Best Design Security Easy To Use 1532 in system programming ® 1149. 1 JTAG boundary scan ® Fast Programming times ® New Capabilities Multiple levels of security ® Affect different mechanisms ® Interconnects are buried ® Multiple security signals ® Scattered and layered Xilinx Web. PACK™or Foundation ISE Software 62

Real. Digital CPLD Advantage 63

Chip Scale Packaging Leadership 17. 6 mm 44 PLCC 12 mm 64 6 mm 8 mm Uses standard IR techniques for mounting to PC board 6 mm Supports high-growth market segments: Communications, Computers, Consumer, especially wireless 56 CP 12 mm 132 CP 17. 6 mm 44 VQFP 8 mm

Lower Power = Smaller Packages • 56 -Ball 0. 5 mm CSP • Provides 44 I/O’s – 0. 5 mm pitch • 36 mm 2 footprint • Ideal for handheld & portable applications – – PDAs Portable PCs Cellular Phones Telecom & Networking Equipment – Network Appliances 65

Best Package Offering for High Volume Applications CP 56 (6 x 6 mm) Smallest form factor CP 132 (8 x 8 mm) chip scale packages Optimized packaging • Smallest size chip scale • Highest performance BGA VQ 44 (10 x 10 mm) VQ 100 (14 x 14 mm) • Highest I/O count • Small size FT 256 (17 x 17 mm) PC 44 (16. 5 x 16. 5 mm) TQ 144 (20 x 20 mm) • Lowest cost flat pack Small form factor, highest performance, BGA packages FG 324 (23 x 23 mm) PQ 208 (28 x 28 mm) Package widths drawn to scale. 66

Cool. Runner-II Family Overview 67

PDA: Cool. Runner Reference Design Example Flash SRAM Battery Compa ct Flash y SMBus Ir. DA P Microproces sor UART LCD Indicates a Cool. CORE 68 Docking Dockin Cradle g Cradle SPI Keypa d LED Touch Screen

Exploiting Our Technology Lead Feature Size (micron) 0. 35 0. 25 CPLDs 0. 18 Clipper 0. 13 FPGAs Schooner 0. 09 0. 07 2000 69 2001 2002 2003 2004 2005

XCR 3000 XL & XC 2 C Low Power Features Open Up New Applications Portable / Consumer PDAs Cell phones MP 3 players Laptops Docking stations Battery powered scanners PDA add-on modules Digital cameras Portable dictation systems Gas meters Handheld meters Smart Card Readers Payphones Medical Portable syringe pump Home monitoring system Blood analyzer 70 Telecom “Neighborhood” Multiplexors Bay Stations Routers Multiplexors PBXs WLAN Central office switches Speech recognition systems PC Peripheral PCMCIA cards Portable computer displays White board scanners Memory cards High Performance Workstations and servers Video graphics cards Storage Systems

One Ultimate CPLD Solution for All Designs Low Cost High Performance 0. 18µ = small die 3. 0 ns TPD, FMAX 385 Mhz size Improved features Lowest cost Storage Systems, packaging Set-Top Box, Cell Routers 71 phone Lowest Power 9. 9 m. W 16µA typical standby Handheld, Portable Equipment

IQ CPLDs for Industrial and Automotive Applications

Introducing IQTM Products • Why IQ? – New range of devices with an extended Industrial Temperature option – Consists of CPLD and FPGA families already available in I Grade - and the addition of selected devices with an extended temperature ‘Q’ grade option – IQ - it’s the intelligent choice for Automotive designers!! • For FPGAs Q grade means: – -40°C to +125°C Junction Temperature • Ambient = the temperature of the air surrounding the device For CPLDs Q Grade means: –Junction tois+125°C Ambient Temperature -40°C = the temperature of the die in the package 73

Industrial and Automotive CPLDs Densit y 512 mc • Low power 2. 5 V • 5 V tolerant • Small packaging 288 m c • Lowest cost 3. 3 V • 5 V tolerant • Small packaging 3. 3 V 74 • 3. 3 V tolerant • Small packaging • Up to 4 I/O banks 2. 5 V Core Voltage • • • Lowest power Highest speed Advanced features Additional security Smallest packages Lowest cost 3. 3 V tolerant 1. 5 V compatible Up to 4 I/O banks 1. 8 V

CPLD Software Improvements in 6. 1 • Ease of use – Improved CPLD process flow • Single process (Implement Design) will pull the design through the entire fitting process • Granular control still possible for power users by expanding individual processes CPLD Software Update and – New design creation aids • Online Support New project wizard leads the user through the project creation process • Add existing source / Create new source processes - assist in getting started faster – Centralized process properties menu • Web Update – File Numberin utility checks for service Built Here 75

Xilinx Online Software Solutions • Web-deliverable desktop and online design solutions for new, high volume markets • Industry’s broadest PLD product offering in a single downloadable solution • Enables fastest time-to-market – Easy to use design tools – Easy to obtain via the web – No license required • Software upgrades available for online purchase 76

ISE 6. 1 i Software Improvements Ease of Use • Improved CPLD process flow – Single process (Implement Design) will pull the design through the entire fitting process – Detailed control still possible for power users by expanding individual processes • New design creation aids – New project wizard leads the user through the project creation process – Add existing source / create new source processes - assist in getting started faster • Centralized process properties 77

ISE 6. 1 i Software Improvements • Web updates – Built in utility checks for service packs and supplemental CPLD updates – Downloads and installs update in single step 78

ISE 6. 1 i Software Improvements • HTML report improvements – Integrated browser in the project navigator environment – Addition of the timing report to HTML format – Improved graphical presentation and equation representation • CPLD support in PACE Pin Assignment and Constraint Editor 79

What’s New in ISE 6. 1 i • Cool. Runner-II – Supported in XPower • Saturn support – All devices in all ISE configurations – Supported in XPower • ISE Web. PACK availability – Web release on Sept 22 – Free CDs available from the Xilinx Online Store • Shipping charges apply – 3, 400 downloads per month and 80 growing!

Buy Products Online • Links to the Xilinx e. Commerce page From Web. FITTER From Web. PACK 81

Additional Web Based Information • For additional Cool. Runner-II product information http: //www. xilinx. com/products/coolrunner 2 • For other Xilinx CPLD related product information http: //www. xilinx. com/products/cpldsolutions • For Cool. Runner-II resource CD http: //www. xilinx. com/forms/coolrunner_literature 82

CPLD Software Improvements in 6. 1 • Ease of use – Improved CPLD process flow • Single process (Implement Design) will pull the design through the entire fitting process • Granular control still possible for power users by expanding individual processes Customer Success aids – New design creation Stories • New project wizard leads the user through the project creation process • Add existing source / Create new source processes - assist in getting started faster – Centralized process properties menu • Web Update – File Numberin utility checks for service Built Here 83

CPLD Success Stories Customer 1 Design Win Factors High Performance Market: Time to Market Application: Digital Audio Fit in Existing Flow Package offering Automotive Broadcast Car 5 v & 3. 3 v Device: Low cost Competition: Lattice Low power Reasons: Radio XC 9572 XL-10 TQ 100 I Pin Locking Pricing Easy to use software 84

CPLD Success Stories Customer 2 Design Win Factors High Performance Market: Time to Market Application: Switching Host Board Fit in Existing Flow Datacom Processor Package offering 5 v & 3. 3 v Devices: XC 95144 XL-10 TQ 100 C Low cost Competition: ASIC Low power Reasons: High performance Pin-locking Flexible interface I/Os 85

CPLD Success Stories Customer 3 Design Win Factors High Performance Time to Market Fit in Existing Flow Market: Consumer Application: MP 3 Player Package offering Device: 5 v & 3. 3 v Competition: None, no one could Low cost Low power XCR 3032 A-VQ 44 C meet low power Reasons: Low power Low Cost, small package 86 software Web-based

CPLD Success Stories Customer 4 Design Win Factors High Performance Market: Time to Market Application: Fingerprint Point-of-Sale Fit in Existing Flow Package offering Consumer Terminal 5 v & 3. 3 v Device: XC 95216 Low cost Competition: None Low power Reasons: On-the-fly changes 133 MHz performance Pin-locking Superior technical support 87

CPLD Success Stories Customer 5 Design Win Factors High Performance Market: Commercial Time to Market Application: Hand-held Cable TV Fit in Existing Flow Package offering Tester 5 v & 3. 3 v Device: XC 95288 XL Low cost Competition: Quicklogic Low power Reasons: Design Flexibility Price Performance 88

CPLD Success Stories Customer 6 Design Win Factors High Performance Time to Market Fit in Existing Flow Package offering 5 v & 3. 3 v Low cost Low power Market: Telecom Application: Voice Synthesis Server Module Device: XCR 3128 Competition: Lattice Reasons: Power! 89

CPLD Success Stories Customer 7 Design Win Factors High Performance Time to Market Fit in Existing Flow Package offering Market: Instrumentation Application: Microcontroller Emulator 5 v & 3. 3 v Low cost Low power Device: XCR 3128 VQ 100 C Competition: Altera Reasons: 90 Power Performance

5 V Motor Control Test Equipment Security Systems Cable Modems Car Nav. Systems Cash Registers Surveillance cameras Set Top Boxes Access Controls Fax Machines Gaming Machines Industrial Control 3. 3 V Tape Drives Power Supplies Modems Access Controls Fax Machines Gaming Machines Industrial Control DAB Car Radios TFT LCD Interface Radio Comms Train Controller Slot Machine Digital Printer 2. 5 V Telecomm Base Stations Encoders Decoders DECT Phones Line Cards Industrial Control LOW POWER 3. 3 V Remote Controls Digital Cameras PDAs Smart Phones Test Equipment Web Pads Medical Equipment Label Printers Mobile phone add-ons MP 3 Players Web pads Payphones Smart Card Readers Hand Held Games USB Applications Utility Meters Data Logger LOW POWER 1. 8 V Portable PDAs Remote Controls Test Equipment Medical Consumer Cell Phones MP 3 Players Set Top Box Hand Held Games High Speed Telecom Switches Routers XC 9500 • 5 v, 36 -288 macrocells • Low Cost • 5 ns / 200 MHz • Best Pin Locking • JTAG • High Endurance (10, 000 program cycles) 91 • 3. 3 v, 36 -288 macrocells • Low Cost • Best Pin Locking • JTAG • High Performance • High Endurance • 5 ns / 200 MHz • 2. 5 v, 36 - 288 macrocells • Low Cost • Best Pin Locking • JTAG • High Performance • High Endurance • 20 year data retention • 4 ns / 250 MHz • 3. 3 v, 32 -512 macrocells • 1. 8 v, 32 -512 macrocells • Ultra Low Power • Schmitt Trigger Inputs • JTAG • Cool. CLOCK, Data. Gate • Logic Flexibility • 3. 5 ns / 303 MHz • 5 ns / 200 MHz • Static power <100 u. A • 20 year data retention • I/Os - LVTTL, LVCMOS SSTL & HSTL • 5 V tolerant I/Os

Xilinx CPLD Summary • XC 9500/XL/XV fast, higher voltage, low-cost – For mainstream 5 v, 3. 3 v & 2. 5 v designs – Great architectural features (ISP, JTAG, pin-locking) • Coolrunner XPLA 3 low power Pioneering low power 3. 3 v product with 5 v tolerant I/O – Lowest power 3. 3 v CPLD - 3 x better than nearest 3. 3 v competitor – • Cool. Runner-II High Performance and Low Power Higher Performance & High Speed (385 MHz) at 1. 8 V – Enhanced clocking & I/O feature set – Lowest power consumption • Data. GATE for even lower power operation – 92