Integration and Automation KEY to Productivity Boost in Analog and Mixed Signal Designs Sarah Xu Managing Director of China Operations Magma Design Automation, Inc.
World is Mixed Signal…And Integrated Signal Talk Capture Create 17 March 2018 - Magma Confidential - 2 Listen Watch
Mixed Signal = Digital + Analog/Custom The International Technology Roadmap for Semiconductors (ITRS) The bleeding edge of ANALOG design is 90 nm, and many are trapped at 130 and 250 nm (5 to 10 year old technology!) 17 March 2018 - Magma Confidential - 3 The cutting edge of DIGITAL design is 45 nm. Active tape outs have been done.
Outline • The Evolution of Digital Tools • The Evolution of Analog Tools • The Requirements for Analog Automation • Mixed Signal Considerations • Magma 2. 0 – Titan 17 March 2018 - Magma Confidential - 4
Outline • The Evolution of Digital Tools • The Evolution of Analog Tools • The Requirements for Analog Automation • Mixed Signal Considerations • Magma 2. 0 – Titan 17 March 2018 - Magma Confidential - 5
Evolution of Digital Tools • Capture design by hand crafting • Capture design by gate level schematics • Functional and timing • Functional verification through event driven logic verification by visual simulation inspection • Implementation by hand drawing 1960 s 17 March 2018 - Magma Confidential - 6 • Timing verification by STA 1970 s • Capture design by RTL • Automated logic synthesis • Automated place and route 1980 s
Outline • The Evolution of Digital Tools • The Evolution of Analog Tools • The Requirements for Analog Automation • Mixed Signal Considerations • Magma 2. 0 – Titan 17 March 2018 - Magma Confidential - 7
Evolution of Analog Tools • Capture design by hand crafting • Capture design by gate level schematics • Functional verification • Functional and timing verification through visual through event driven logic simulation inspection • Implementation by hand drawing 1960 s • Capture design by hand crafting • Functional and timing verification through test bench in real world setting 17 March 2018 - Magma Confidential - 8 • Capture design by RTL • Automated logic synthesis • Timing verification by STA • Automated place and route 1970 s 1990 s • Analog simulation via SPICE • Capture design by transistor level schematics
Limitation of Today’s Analog Tools • Most of today's analog tools were conceived in 1990 s • The underlying architectures were never intended to support the sophisticated demands of a mixed-signal design environment • Today's analog design and verification tools are essentially limited to transistor-level schematics • Very limited success w. r. t. automation • Representing analog functionality at a high-level of • • abstraction and then using these representations to generate transistor-level equivalents Automatically optimizing analog circuits Automatically placing-and-routing analog circuits 17 March 2018 - Magma Confidential - 9
Digital Design is Automated, Reusable Digital Custom Digital Cells ADC SERDES PLL always @ (posedge sm_clock) begin if (reset == 1'b 1) current_state <= 2'b 00; else current_state <= next_state; end always @ (current_state or sm_in) begin // default values sm_out = 1'b 1; next_state = current_state; case (current_state) idle: sm_out = 1'b 0; if (sm_in) next_state = 2'b 11; write: sm_out = 1'b 0; if (sm_in == 1'b 0) next_state = 2'b 10; read: if (sm_in == 1'b 1) next_state = 2'b 01; wait: if (sm_in == 1'b 1) next_state = 2'b 00; endcase endmodule Synthesis, RTL & Route Place Turnaround Time 2 Days 17 March 2018 - Magma Confidential - 10 Synthesized Digital Logic Memory
Analog / Custom Design is NOT Automated, NOT Reusable Digital Custom Digital Cells ADC SERDES Analog PLL Synthesized Digital Logic Memory IP Process Migration Turnaround Time 6 -12 Months Integration Synthesis, Place & Route Turnaround Time 4 -8 Weeks Turnaround Time 2 Days Transcievers, SERDES… Turnaround Time 3 -6 Months 17 March 2018 - Magma Confidential - 11
Why? Analog/Custom Design System Design Excel, C, Paper, Verilog A/AMS C, Matlab, Spice Circuit Design Excel, Matlab, Paper… Schematic Capture, Spice Physical Design Manual Design & Constraints Placement, Routing, Extraction, Spice For every new process node, designs have to be re-created by-hand from scratch It’s a Very Hard Problem To Solve! 17 March 2018 - Magma Confidential - 12 Accuracy ? Automation ? Re-use ? Ease of Use ? Compatibility ?
Mixed Signal = Digital + Analog/Custom The International Technology Roadmap for Semiconductors (ITRS) The bleeding edge of ANALOG design is 90 nm, and many are trapped at 130 and 250 nm (5 to 10 year old technology!) 17 March 2018 - Magma Confidential - 13 The cutting edge of DIGITAL design is 45 nm. Active tape outs have been done.
Outline • The Evolution of Digital Tools • The Evolution of Analog Tools • The Requirements for Analog Automation • Mixed Signal Considerations • Magma 2. 0 – Titan 17 March 2018 - Magma Confidential - 14
Wish List for Next Generation Analog Tools • The ability to specify an analog function at a high level of • • abstraction and to then automatically translate this representation into its transistor-level equivalent The ability to automatically perform analog refinement and optimization The ability to automatically place analog components on the IC The ability to automatically route analog components on the IC The capability to automate the migration process for an analog design from one process/technology node to another and from one foundry to another 17 March 2018 - Magma Confidential - 15
Outline • The Evolution of Digital Tools • The Evolution of Analog Tools • The Requirements for Analog Automation • Mixed Signal Considerations • Magma 2. 0 – Titan 17 March 2018 - Magma Confidential - 16
Wish List for Next Generation Mixed Signal Tools • Analog and digital design and verification engines should employ a unified database • The environment must provide extreme capacity and performance • Such as loading the entire full-chip database in a minute or less and re-drawing all of the analog and digital layers in seconds • The environment must support extremely accurate parasitic extraction and full-chip mixedsignal simulation and analysis • At the chip-finishing stage, the environment must support automatic global routing 17 March 2018 - Magma Confidential - 17
Outline • The Evolution of Digital Tools • The Evolution of Analog Tools • The Requirements for Analog Automation • Mixed Signal Considerations • Magma 2. 0 – Titan 17 March 2018 - Magma Confidential - 18
Magma 2. 0: Mixed-Signal Design Analog IP Process Migration * Integrated Simulation Environment Including Waveform Editor Schematic Editor Layout Editor Shape Based, Constraint Driven Routing Mixed Signal Physical Constraints * Digital & Analog Integration Integrated Full Chip LVS, DRC and Extraction Full Chip Timing / Signal Noise Analysis United Custom And Digital Database Titan: Mixed-Signal Platform 17 March 2018 - Magma Confidential - 19 * Beta / Limited production now Full Production Q 3 -08
Driving the Shift to Titan • Accuracy • Production proven Fine. Sim integrated simulation environment • Automation • Analog IP process migration automation • Integration Ease of Use • • Integration to support digital, custom, analog flows seamlessly • Integration with Fine. Sim, Talus, Quartz DRC/LVS Faster time to tapeout • • Up to 10 x speed and capacity advantage over old solutions Speed and capacity to iterate quickly and close • Smooth Migration Path • • Open. Access Compatibility Easily transition existing design to Titan 17 March 2018 - Magma Confidential - 20
Titan: The Only Mixed-Signal Platform Embedded Talus 17 March 2018 - Magma Confidential - 21
Titan: High Speed, High Capacity Layout & Schematic Editor • • • Responsive all-layer redraw, pan & zoom Integrated GUI with menus, hotkeys & tear-off panels Fully scriptable Tcl/Tk interface Cell hierarchy browser Edit-in-place correct across hierarchy Full cross-probing: schematics, DRC errors & parasitics Example: Layout Editing of 42 GB GDSII Design • • 17 March 2018 - Magma Confidential - 22 Full Chip Open 4 min Redraw 8 sec Zoom In by 2 4 sec Pan time to random points 7 sec
Titan Accuracy Fine. Sim SPICE : Fastest Spice Simulator • • Unified Single Executable Simulator • Native-Parallel™ Technology (NPT) Fine. Sim SPICE (Full SPICE with NPT) • Increased analog SPICE capacity • Single-CPU Fine. Sim SPICE 3 -10 X Faster Than Other SPICE Engines • Fine. Sim Pro (Fast SPICE with NPT) • 1 -3% SPICE Accuracy 17 March 2018 - Magma Confidential - 23 Integrated Analog Simulation Environment • Fine. Sim Customer Success • Toshiba, Maxim, Faraday, AMD, Silicon. Blue, STARC, Sigma Design. . .
Fully Integrated Custom/Digital Analysis • Sign-off Quality Analysis • DRC, LVS • Extraction, Timing • Noise, Power • DFM, Yield • Complete Integration • Push-button “invocation” • Cross-probing debug • Fast incremental iteration 17 March 2018 - Magma Confidential - 24
Unified, Shape-Based Custom & Chip Finishing Router • • • Shape-based flexibility Built for modern nm geometries and design sizes Supports Schematic driven Layout • • Automates critical signal handling • • Custom routing constraints Net length control (min, max, match T-line) Signal shielding (parallel, tandem, coax) Differential pair support Analog-digital global routing • • Ensures timing consistency across digital and custom routing regions Speed and capacity to easily handle the largest mixed-signal chips 17 March 2018 - Magma Confidential - 25 Magma’s Unified Routing System Timing-Driven Global Router Titan Custom Shape Router Talus Digital Router
Titan: Open Architecture GDS Live Link PDK 3 rd Party Tools Volcano OA LEF / DEF PCells™ / Py. Cells™ OA Verilog GDS 17 March 2018 - Magma Confidential - 26 SPICE
Analog IP Design & Process Migration Original Design Time Process Migration Time Circuit Design 80 days 50 days Layout 60 days IP process migration requires almost as much circuit design and layout time as the original rev! *Source: Rambus, www. scdsource. com/article. php? id=39 17 March 2018 - Magma Confidential - 27
Modern Approach to Analog IP Process Migration • Write a specification on a computer • Analyze the resulting circuit • “Implement and Optimize” it • Re-Use it • • • Change specifications Change process nodes Do in minutes what would take days and months “the old way” Design Constraints Design & Foundry Specific Library 17 March 2018 - Magma Confidential - 28 Analog IP Process Migration Schematic & Layout Constraints
Revolutionary Analog IP Design & Process Migration Titan Analog. Ware Sabio Technology Matlab Specs Standard Custom Integrated Simulation (Fine. Sim) Mixed Signal Physical Constraints Titan Analog Optimization (Circuit & Physical) Schematic / Layout Editor Proc ess Mod els Process Compiler Sized and Verified Design PD K 17 March 2018 - Magma Confidential - 29
Titan: Process Migration Results Without Titan AO With Titan AO PCI-E IO driver, 2. 5 GHz (17 corners) 2 weeks 1 hour Bandgap (33 corners) 3 weeks 5 min 6. 4 GHz SERDES Linear Equalizer (9 corners) 2 weeks 5 min 1. 5 GHz, 1 V PLL (9 corners) 2 months 1 hour 12 bit pipeline, 100 MS, system + op-amps (5 corners) 2 weeks 1 hour Order Of Magnitude Faster Porting While Achieving Equal Or Better Performance 17 March 2018 - Magma Confidential - 30
Titan: Integrated Mixed-Signal Platform • Mixed-Signal Platform • Embedded Talus • Shape-Based Routing • Mixed-Signal Verification • Analog Block • Design & Migration • Speed and Capacity • Compatibility • Accommodate legacy data • OA Compatible 17 March 2018 - Magma Confidential - 31 + + Mixed-Signal Design
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