inst eecs berkeley edu cs 61 c su 06 CS

inst. eecs. berkeley. edu/~cs 61 c/su 06 CS 61 C : Machine Structures Lecture #17: CPU Design II – Control 2006 -07 -26 Andy Carle CS 61 C L 17 Control (1) A Carle, Summer 2006 © UCB

Anatomy: 5 components of any Computer Personal Computer Processor This week Control (“brain”) Datapath (“brawn”) Memory (where programs, data live when running) Devices Input Output Keyboard, Mouse Disk (where programs, data live when not running) Display, Printer CS 61 C L 17 Control (2) A Carle, Summer 2006 © UCB

Review: A Single Cycle Datapath • Rs, Rt, Rd, Imed 16 connected to datapath • We have everything except control signals Instruction<31: 0> Mem. Wr Clk Memto. Reg 0 32 Data In 32 ALUSrc Rs Rd Imm 16 Wr. En Adr Data Memory 32 Mux 32 1 <0: 15> Extender 16 ALU bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 imm 16 Rt Zero ALUctr Mux bus. W 32 Clk <11: 15> Rt Reg. Dst 1 Mux 0 Rs Rt Reg. Wr 5 5 5 <16: 20> Rd Instruction Fetch Unit <21: 25> n. PC_sel 1 Ext. Op CS 61 C L 17 Control (3) A Carle, Summer 2006 © UCB

An Abstract View of the Critical Path (Load Operation) = Delay clock through PC (FFs) + • This affects how fast you Instruction Memory’s Access Time + can clock your Register File’s Access Time, + PC ALU to Perform a 32 -bit Add + Data Memory Access Time + Ideal Stable Instruction Time for Register File Write Memory Rd Rs Rt 5 5 5 32 Clk PC A CS 61 C L 17 Control (4) Clk Rw Ra Rb 32 32 -bit 32 Registers B ALU Next Address Instruction Address Imm 16 32 Data 32 Address Data In Ideal Data Memory Clk A Carle, Summer 2006 © UCB

Recap: Meaning of the Control Signals 0 PC <– PC + 4 1 PC <– PC + 4 + “n”=next {Sign. Ext(Im 16) , 00 } • Later in lecture: higher-level connection between mux and branch cond • n. PC_MUX_sel: n. PC_MUX_sel Inst Adr Memory Adder imm 16 PC Mux Adder PC Ext CS 61 C L 17 Control (5) 00 4 Clk A Carle, Summer 2006 © UCB

Recap: Meaning of the Control Signals • Ext. Op: “zero”, “sign” ° Mem. Wr: 1 write memory ° Memto. Reg: 0 ALU; 1 Mem • ALUsrc: 0 reg. B; 1 immed ° Reg. Dst: 0 “rt”; 1 “rd” • ALUctr: “add”, “sub”, “or”Reg. Wr: 1 write register ° Reg. Dst ALUctr Mem. Wr Memto. Reg = 32 32 Wr. En. Adr Data In Data Clk Memory Ext. Op ALUSrc 0 Mux ALU CS 61 C L 17 Control (6) Mux Extender Equal Rd Rt 1 0 Rs Rt Reg. Wr 5 5 5 bus. A Rw Ra Rb bus. W 32 32 32 -bit 32 Registers bus. B 0 32 Clk 1 imm 16 32 16 1 A Carle, Summer 2006 © UCB

RTL: The Add Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits add rd, rs, rt • MEM[PC] Fetch the instruction from memory • R[rd] = R[rs] + R[rt] The actual operation • PC = PC + 4 Calculate the next instruction’s address CS 61 C L 17 Control (7) A Carle, Summer 2006 © UCB

Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction = MEM[PC] • same for all instructions Inst Memory Adr Instruction<31: 0> n. PC_MUX_sel Adder imm 16 PC Mux Adder PC Ext CS 61 C L 17 Control (8) 00 4 Clk A Carle, Summer 2006 © UCB

The Single Cycle Datapath during Add 31 26 21 op rs 16 11 rt 6 rd shamt • R[rd] = R[rs] + R[rt] 5 Zero ALU 16 Extender imm 16 1 32 Rd Imm 16 Memto. Reg = 0 Mem. Wr = 0 0 32 Data In 32 ALUSrc = 0 Rs Clk Wr. En Adr 32 Mux bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt <0: 15> 5 ALUctr = Add Rt <11: 15> 5 Rs Instruction Fetch Unit Mux 32 Clk 1 Mux 0 Reg. Wr = 1 bus. W Rt Instruction<31: 0> <16: 20> Reg. Dst = 1 Rd funct <21: 25> n. PC_sel= +4 0 1 Data Memory Ext. Op = x CS 61 C L 17 Control (9) A Carle, Summer 2006 © UCB

Instruction Fetch Unit at the End of Add • PC = PC + 4 • This is the same for all instructions except: Branch and Jump Inst Memory Adr Instruction<31: 0> n. PC_MUX_sel PC Mux Adder imm 16 Adder CS 61 C L 17 Control (10) 0 00 4 1 Clk A Carle, Summer 2006 © UCB

Single Cycle Datapath during Or Immediate? 31 26 op 21 rs 16 0 rt immediate • R[rt] = R[rs] OR Zero. Ext[Imm 16] Instruction<31: 0> ALU 16 Extender imm 16 Zero Mem. Wr = 1 32 ALUSrc = 0 32 Data In 32 Clk Imm 16 Memto. Reg = Wr. En Adr 32 Mux bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rs Rd <0: 15> 5 Rt ALUctr = <11: 15> Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = bus. W Rt <16: 20> Reg. Dst = Rd Instruction Fetch Unit <21: 25> n. PC_sel = 1 Data Memory Ext. Op = CS 61 C L 17 Control (11) A Carle, Summer 2006 © UCB

Single Cycle Datapath during Or Immediate? 31 26 op 21 16 rs 0 rt immediate • R[rt] = R[rs] OR Zero. Ext[Imm 16] Rs Rt 5 5 ALU 16 Extender imm 16 Zero 1 32 Imm 16 Memto. Reg = 0 Mem. Wr = 0 0 32 Data In 32 ALUSrc = 1 Rs Rd Clk Wr. En Adr 32 Mux bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Mux 32 Clk Rt ALUctr = Or <0: 15> 1 Mux 0 Reg. Wr = 15 bus. W Clk <11: 15> Rt <16: 20> Reg. Dst = 0 Rd Instruction Fetch Unit <21: 25> n. PC_sel= +4 Instruction<31: 0> 1 Data Memory Ext. Op = 0 CS 61 C L 17 Control (12) A Carle, Summer 2006 © UCB

The Single Cycle Datapath during Load? 31 26 21 op rs 16 0 rt immediate • R[rt] = Data Memory {R[rs] + Sign. Ext[imm 16]} Instruction<31: 0> 5 bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt Zero 32 Imm 16 Memto. Reg = Mem. Wr = 0 32 Data In 32 ALUSrc = Rd Clk Mux ALU 16 Extender imm 16 1 Rs <0: 15> 5 ALUctr = Rt <11: 15> 5 Rs Mux 32 Clk 1 Mux 0 Reg. Wr = bus. W Rt <21: 25> Reg. Dst = Rd Instruction Fetch Unit <16: 20> n. PC_sel= 1 Wr. En Adr Data Memory 32 Ext. Op = CS 61 C L 17 Control (13) A Carle, Summer 2006 © UCB

The Single Cycle Datapath during Load 31 26 21 op rs 16 0 rt immediate • R[rt] = Data Memory {R[rs] + Sign. Ext[imm 16]} 5 ALUctr = Add Rt bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt Zero 32 Data In 32 ALUSrc = 1 Rd Imm 16 Memto. Reg = 1 Mem. Wr = 0 0 Clk Mux ALU 16 Extender imm 16 1 Rs 32 Mux 32 Clk 5 Rs <0: 15> 1 Mux 0 Reg. Wr = 1 5 bus. W Clk <11: 15> Rt <16: 20> Reg. Dst = 0 Rd Instruction Fetch Unit <21: 25> n. PC_sel= +4 Instruction<31: 0> 1 Wr. En Adr Data Memory 32 Ext. Op = 1 CS 61 C L 17 Control (14) A Carle, Summer 2006 © UCB

The Single Cycle Datapath during Store? 31 26 op 21 rs 16 0 rt immediate • Data Memory {R[rs] + Sign. Ext[imm 16]} = R[rt] 1 Mux 0 Rs Rt 5 5 Reg. Wr = 5 Rt ALUctr = bus. A 16 Extender imm 16 1 32 ALUSrc = 0 32 Data In 32 Clk Memto. Reg = Wr. En Adr 32 Mux Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Mux 32 Clk Imm 16 Zero Mem. Wr = ALU bus. W Rs Rd <0: 15> Clk <11: 15> Rt <16: 20> Reg. Dst = Rd Instruction Fetch Unit <21: 25> n. PC_sel = Instruction<31: 0> 1 Data Memory Ext. Op = CS 61 C L 17 Control (15) A Carle, Summer 2006 © UCB

The Single Cycle Datapath during Store 31 26 op 21 rs 16 0 rt immediate • Data Memory {R[rs] + Sign. Ext[imm 16]} = R[rt] 1 32 0 32 Data In 32 ALUSrc = 1 Rs Rd Clk Wr. En Adr Data Memory 32 Mux 16 Extender imm 16 Imm 16 Memto. Reg = x Zero Mem. Wr = 1 ALU bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt Mux 32 Clk ALUctr = Add Rs Rt 5 5 <0: 15> 1 Mux 0 Reg. Wr = 0 5 bus. W Clk <11: 15> Rt <16: 20> Reg. Dst = x Rd Instruction Fetch Unit <21: 25> n. PC_sel= +4 Instruction<31: 0> 1 Ext. Op = 1 CS 61 C L 17 Control (16) A Carle, Summer 2006 © UCB

The Single Cycle Datapath during Branch? 31 26 op 21 16 rs 0 rt immediate • if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 Instruction<31: 0> Data In 32 ALUSrc = 0 32 Clk Wr. En Adr 32 Mux 32 Imm 16 Memto. Reg = x Zero Mem. Wr = ALU 16 Extender imm 16 1 Rs Rd <0: 15> bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 <11: 15> 5 Rt ALUctr = Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = bus. W Rt <16: 20> Reg. Dst = Rd Instruction Fetch Unit <21: 25> n. PC_sel= 1 Data Memory Ext. Op = CS 61 C L 17 Control (17) A Carle, Summer 2006 © UCB

The Single Cycle Datapath during Branch 31 26 op 21 16 rs 0 rt immediate • if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 Instruction<31: 0> 32 0 32 Data In 32 ALUSrc = 0 Rs Rd Clk Wr. En Adr 32 Mux 1 <0: 15> 16 Extender imm 16 Imm 16 Memto. Reg = x Zero Mem. Wr = 0 ALU bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 <11: 15> 5 Rt ALUctr =Sub Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = 0 bus. W Rt <16: 20> Reg. Dst = x Rd Instruction Fetch Unit <21: 25> n. PC_sel= “Br” 1 Data Memory Ext. Op = x CS 61 C L 17 Control (18) A Carle, Summer 2006 © UCB

Instruction Fetch Unit at the End of Branch 31 26 21 op rs 16 rt 0 immediate • if (Zero == 1) then PC = PC + 4 + Sign. Ext[imm 16]*4 ; else PC = PC + 4 Inst Memory n. PC_sel Adr Zero n. PC_MUX_sel Adder 0 imm 16 PC Mux Adder CS 61 C L 17 Control (19) 00 4 1 Instruction<31: 0> • What is encoding of n. PC_sel? • Direct MUX select? • Branch / not branch • Let’s pick 2 nd option Q: What logic gate? Clk A Carle, Summer 2006 © UCB

Step 4: Given Datapath: RTL -> Control Instruction<31: 0> Rd <0: 15> Rs <11: 15> Rt <16: 20> Op Fun <21: 25> Adr <0: 5> <26: 31> Inst Memory Imm 16 Control n. PC_sel Reg. Wr Reg. Dst Ext. Op ALUSrc ALUctr Mem. Wr Memto. Reg Zero DATA PATH CS 61 C L 17 Control (20) A Carle, Summer 2006 © UCB

A Summary of the Control Signals (1/2) inst Register Transfer ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = Reg. B, ALUctr = “add”, Reg. Dst = rd, Reg. Wr, n. PC_sel = “+4” SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = Reg. B, ALUctr = “sub”, Reg. Dst = rd, Reg. Wr, n. PC_sel = “+4” ORi R[rt] <– R[rs] + zero_ext(Imm 16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, Reg. Dst = rt, Reg. Wr, n. PC_sel =“+4” LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm 16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, Memto. Reg, Reg. Dst = rt, Reg. Wr, n. PC_sel = “+4” STORE MEM[ R[rs] + sign_ext(Imm 16)] <– R[rs]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, Mem. Wr, n. PC_sel = “+4” BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm 16)] || 00 else PC <– PC + 4 n. PC_sel = “Br”, ALUctr = “sub” CS 61 C L 17 Control (21) A Carle, Summer 2006 © UCB

A Summary of the Control Signals (2/2) See Appendix A func 10 0000 10 0010 We Don’t Care : -) op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 ALUSrc Memto. Reg. Write Mem. Write add 1 0 0 1 0 sub 1 0 0 1 0 ori 0 1 0 lw 0 1 1 1 0 sw x 1 x 0 1 n. PCsel Jump Ext. Op ALUctr<2: 0> 0 0 x Add 0 0 x Subtract 0 0 0 Or 0 0 1 Add Reg. Dst 31 26 21 16 R-type op rs rt I-type op rs rt J-type op 11 CS 61 C L 17 Control (22) rd beq x 0 0 1 0 x 0 1 x xxx Subtract 6 shamt immediate target address jump x x x 0 0 0 funct add, sub ori, lw, sw, beq jump A Carle, Summer 2006 © UCB

Administrivia • Project 2 Due Friday • HW 5 Now Available CS 61 C

The Single Cycle Datapath during Jump 31 J-type 26 25 0 op jump target address • New PC = { PC[31. . 28], target address, 00 } Instruction<31: 0> Jump= <0: 25> Data In 32 ALUSrc = 0 32 Clk Wr. En Adr 32 Mux 32 <0: 15> 1 <11: 15> 16 Extender imm 16 Rs Rd Imm 16 TA 26 Memto. Reg = Zero Mem. Wr = ALU bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 <16: 20> 5 Rt ALUctr = Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = bus. W Rt <21: 25> Reg. Dst = Rd Instruction Fetch Unit n. PC_sel= 1 Data Memory Ext. Op = CS 61 C L 17 Control (24) A Carle, Summer 2006 © UCB

The Single Cycle Datapath during Jump 31 J-type 26 25 0 op jump target address • New PC = { PC[31. . 28], target address, 00 } Instruction<31: 0> Jump=1 <0: 25> Data In 32 ALUSrc = x 0 32 Clk Wr. En Adr 32 Mux 32 <0: 15> 1 <11: 15> 16 Extender imm 16 Rs Rd Imm 16 TA 26 Memto. Reg = x Zero Mem. Wr = 0 ALU bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 <16: 20> 5 Rt ALUctr =x Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = 0 bus. W Rt <21: 25> Reg. Dst = x Rd Instruction Fetch Unit n. PC_sel=0 1 Data Memory Ext. Op = x CS 61 C L 17 Control (25) A Carle, Summer 2006 © UCB

Instruction Fetch Unit at the End of Jump 31 26 25 J-type 0 op jump target address • New PC = { PC[31. . 28], target address, 00 } Jump Inst Memory n. PC_sel Instruction<31: 0> Adr Zero n. PC_MUX_sel Adder 0 imm 16 PC Mux Adder CS 61 C L 17 Control (26) 00 4 How do we modify this to account for jumps? 1 Clk A Carle, Summer 2006 © UCB

Instruction Fetch Unit at the End of Jump 31 26 25 J-type 0 op jump target address • New PC = { PC[31. . 28], target address, 00 } Jump Inst Memory n. PC_sel Instruction<31: 0> Adr Zero imm 16 Mux Adder CS 61 C L 17 Control (27) 1 00 4 (MSBs) 00 Adder 0 1 PC 4 Mux TA 26 n. PC_MUX_sel 0 Clk Query • Can Zero still get asserted? • Does n. PC_sel need to be 0? • If not, what? A Carle, Summer 2006 © UCB

Build CL to implement Jump on paper now Inst 31 Inst 30 Inst 29 Inst 28 Inst 27 Inst 26 Inst 25 Jump Inst 01 Inst 00 CS 61 C L 17 Control (28) A Carle, Summer 2006 © UCB

Build CL to implement Jump on paper now Inst 31 Inst 30 Inst 29 Inst 28 Inst 27 Inst 26 Inst 25 Inst 01 Inst 00 A 0 0 1 0 CS 61 C L 17 Control (29) 2 -input 6 -bit-wide XNOR B Ai 0 0 1 1 6 -input AND Bi XNOR 0 1 1 0 0 0 1 1 Jump A Carle, Summer 2006 © UCB

Peer Instruction<31: 0> Reg. Wr Rs Rt 5 Extender 16 1 32 Clk Imm 16 Mem. Wr Memto. Reg 0 32 Data In 32 ALUSrc Rs Rd Wr. En Adr 32 Mux bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 imm 16 Rt Zero ALUctr Mux 32 Clk 5 ALU bus. W 5 <0: 15> Clk 1 Mux 0 <11: 15> Reg. Dst Rt <21: 25> Rd Instruction Fetch Unit <16: 20> n. PC_sel 1 Data Memory Ext. Op A. Mem. To. Reg=‘x’ & ALUctr=‘sub’. SUB or BEQ? B. ALUctr=‘add’. Which 1 signal is different for all 3 of: ADD, LW, & SW? Reg. Dst or Ext. Op? C. “Don’t Care” signals are useful because we can simplify our Boolean equations? CS 61 C L 17 Control (30) A Carle, Summer 2006 © UCB

And in Conclusion… Single cycle control ° 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. Processor • 5. Assemble the control logic Input ° Control is the hard part ° MIPS makes that easier Control Memory Datapath • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates CS 61 C L 17 Control (31) Output A Carle, Summer 2006 © UCB