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IDEAL-IST Workshop Christos P. Sotiriou, Institute of Computer Science, FORTH. sotiriou@ics. forth. gr 2/6/2003 IDEAL-IST Workshop Christos P. Sotiriou, Institute of Computer Science, FORTH. sotiriou@ics. forth. gr 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 1

FORTH • FORTH - Foundation for Research and Technology - Hellas. – – – FORTH • FORTH - Foundation for Research and Technology - Hellas. – – – – – 2/6/2003 Established in 1983. Internationally recognised R&D centre. 7 institutes, 280 Researchers, 735 Personnel (1999). ~30, 000 E of annual budget. performs high-quality basic research. Development of innovative technologies. founder of many start-ups, FORTHnet is one of them. contributes to the development of Science&Technology parks. collaborates with the University of Crete and other Universities. IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 2

VLSI Group Activities • Packet Switch Architectures (M. Katevenis) – commodity switches. – multi-gigabit VLSI Group Activities • Packet Switch Architectures (M. Katevenis) – commodity switches. – multi-gigabit switching fabrics with backpressure. • Scalable Computing Infrastructures (A. Bilas) – system area networks (SAN). – single-system-image clusters. – networks of autonomous sensors. • Advanced Computing Systems (E. Markatos) – Internet Systems and their Security. – GRID computing and peer-to-peer systems. 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 3

VLSI Group Activities • Network Processing (I. Papaefstathiou) – High-throughput packet processing. – On-the-fly VLSI Group Activities • Network Processing (I. Papaefstathiou) – High-throughput packet processing. – On-the-fly compression and encryption. • System Timing and Synchronisation (C. Sotiriou) – Asynchronous circuit/system design • low-power, low-EMI. – Asynchronous design using commercial EDA tools. 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 4

System Timing Activities • Coordinators of IST Project ASPIDA (IST-2002 -37796). – ASPIDA. • System Timing Activities • Coordinators of IST Project ASPIDA (IST-2002 -37796). – ASPIDA. • (ASynchronous open-source Processor Ip of the Dlx Architecture). • with Politecnico di Torino and Manchester University. – Aim: to develop an open-source, low-power, low-EMI, flexibleinterface processor for embedded applications. • • fully-asynchronous CPU (DLX architecture). may be migrated to any fabrication technology. industrial quality testability (>95%). 2 processor bus interfaces: – WISHBONE: synchronous Open on-chip bus (Open. Cores). – CHAIN: novel asynchronous on-chip bus. 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 5

System Timing Activities • members of the ACi. D-WG (IST-1999 -29119). – Hosted the System Timing Activities • members of the ACi. D-WG (IST-1999 -29119). – Hosted the 3 rd ACi. D Workshop. • Organising the 10 th IEEE ASYNC conference. – More about this at the end! • Other informal research activities: – – 2/6/2003 SOC interconnect design (asynchronous). EDA tool design (mainly synthesis). EDA flow design. Asynchronous FPGAs? IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 6

Asynchronous Technology? • EMI Comparison (ARM 9 vs. AMULET 3) 2/6/2003 IDEAL-IST Workshop, Christos Asynchronous Technology? • EMI Comparison (ARM 9 vs. AMULET 3) 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 7

Asynchronous Technology? • Power Density Comparison (Philips 80 C 51): 2/6/2003 IDEAL-IST Workshop, Christos Asynchronous Technology? • Power Density Comparison (Philips 80 C 51): 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 8

Asynchronous Technology? • Deep Sub. Micron clocked designs: – clock distribution issues • • Asynchronous Technology? • Deep Sub. Micron clocked designs: – clock distribution issues • • clock tree depth clock tree power consumption high Electro. Magnetic Interference (EMI) clock skew; timing closure problems – constant reduction of area reachable in 1 clock cycle – continuous power consumption – Example Designs • DEC Alpha 21264: 30 -40% power to clock tree • ARM 9 TDMI , 220 MHz, 32% power to clock tree • Pentium 4 : 20 pipeline stages, 42 M trans, 66 Watts 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 9

ASPIDA: R&D • R&D activities in ASPIDA: – asynchronous circuit synthesis from standard HDLs. ASPIDA: R&D • R&D activities in ASPIDA: – asynchronous circuit synthesis from standard HDLs. – use of commercial EDA tools for asynchronous design • Cadence, Synopsys based EDA flows. – automated synthesis of asynchronous Control Circuits. • relative timed (fast). • speed independent (robust). – automated synthesis of asynchronous Datapaths. – automated scan chain insertion for ATPG – asynchronous on-chip bus (CHAIN) • low communication latency. • no Signal Integrity problems. 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 10

ASPIDA: Contribution ΑDLX ADLX HARD IP SOFT IP HDL+ flow Typical SOC 2/6/2003 IDEAL-IST ASPIDA: Contribution ΑDLX ADLX HARD IP SOFT IP HDL+ flow Typical SOC 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 11

ASPIDA: CHAIN Interconnect 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 12 ASPIDA: CHAIN Interconnect 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 12

Collaboration/Ideas • Collaboration in using/promoting asynchronous technology. – Using/improving our technology on specific applications: Collaboration/Ideas • Collaboration in using/promoting asynchronous technology. – Using/improving our technology on specific applications: • mobile and embedded systems. • low-power, low-EMI systems. • high performance? scalable asynchronous VLSI systems? • mixed synchronous/asynchronous systems, interfaces and circuits. – Comparing with possible alternatives: • optical clock networks, optical interconnects. – Develop EDA tools for asynchronous design. 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 13

ASYNC 2004 The 10 th IEEE International Symposium on Asynchronous Circuits and Systems HERSONISSOS, ASYNC 2004 The 10 th IEEE International Symposium on Asynchronous Circuits and Systems HERSONISSOS, CRETE, GREECE, 19 -23 April 2004. http: //www. ics. forth. gr/async 2004, http: //www. async 04. gr. 2/6/2003 IDEAL-IST Workshop, Christos P. Sotiriou, ICS-FORTH 14