Henk Corporaal EE department Delft Univ. of Technology h. corporaal@et. tudelft. nl http: //cs. et. tudelft. nl
Topics
MOVE project goals
Architecture design spectrum
Architecture design spectrum
Architecture design spectrum
Architecture design spectrum
From VLIW to TTA
From VLIW to TTA
From VLIW to TTA
Transport Triggered Architecture
TTA structure; datapath details
TTA characteristics
Register pressure
TTA characteristics
Code generation trajectory
TTA compiler characteristics
Code generation for TTAs
Mapping applications to processors
Mapping applications to processors Move framework
Achievements within the MOVE project
Video stretcher board containing TTA
Intelligent datalogger
TTA related research
Ro. D: Register on Demand scheduling
Ro. D compared with early assignment
Ro. D compared with early assignment Impact of decreasing number of registers
Special Functionality: SFUs
Mapping applications to processors
SFUs: fine grain patterns
SFUs: Pattern identification
SFUs: fine grain patterns
SFUs: top-10 patterns (2 ops)
SFUs: conclusions
Source-to. Source transformations
Design transformations
Structure of transformation
Implementation
Experimental results
Partitioning your program for Multiprocessor single chip solutions
Multiprocessor embedded system
Design transformations
Experimental results of partitioner
Global program optimizations
Traditional compilation path
New Compilation Path
Inter-module Register Allocation
Fixed-point conversion: motivation
Fixed-point conversion
Methodology
Link-time code conversion
Experimental Results
Experimental Results
What next? L: design level (e. g. architecture, implementation or realization level) A: application compononents D: dependences between application components N: hardware component C: connections between hardware components
Conclusions / Discussion