Hardware/Software Codesign “Finding right combination of HW/SW resulting in the most efficient product meeting the specification” EE 898 -HW/SW co-design - 1 -
Design productivity gap EE 898 -HW/SW co-design - 2 -
EE 898 -HW/SW co-design 3 - © Lauro Rizzatti Marketing Vice President Emulation & Verification Engineering (EVE) lauro@eve-usa. com
Reuse as a way out - Plus: Increasing ES complexity, time-to-market requirements - Pre-designed standard components to be used. • Standard software components • Standard hardware components Platform-based design EE 898 -HW/SW co-design - 4 -
Platform-based design A platform is a family of architectures satisfying a set of constraints imposed to allow the reuse of hardware and software components. However, a hardware platform is not enough. Quick, reliable, derivative design requires using a platform application programming interface (API) to extend the platform toward application software. In general, a platform is an abstraction layer that covers many possible refinements to a lower level. Platform-based design is a meet-in-the-middle approach: In the top-down design flow, designers map an instance of the upper platform to an instance of the lower, and propagate design constraints [Sangiovanni-Vincentelli, 2002]. EE 898 -HW/SW co-design - 5 -
Iterative approach (1) Guided by performance evaluation EE 898 -HW/SW co-design - 6 -
Mapping Essentially the same with our flow … EE 898 -HW/SW co-design - 7 -
Iterative approach: Spec. C model - Allocation: selecting components - Partitioning: mapping parts of system spec to components - Scheduling: serialize execution EE 898 -HW/SW co-design - 8 -
Overview of design activities • Task level concurrency management Which tasks in the final system? • High level transformations Transformation that are outside the scope of traditional compilers (fixed-point arithmetic floating-point arithmetic) • Hardware/software partitioning Which operation mapped to hardware, which to software? • Compilation (software) Hardware- aware compilation (efficient improved if knowing the hardware) • Scheduling Performed several times, with varying precision • Design space exploration Set of possible designs meeting specifications, chose one. EE 898 -HW/SW co-design - 9 -
Task-level concurrency management Break into small tasks. Granularity: size of tasks (e. g. in instructions) Readable specifications and efficient implementations can possibly require different task structures. Granularity changes Task partitioning does not necessary aim to maximize implementation efficiency. Not one-to-one corresponding between task and spec. Merging or splitting tasks. EE 898 -HW/SW co-design - 10 -
Merging of tasks Reduced overhead of context switches, More global optimization of machine code, Reduced overhead for inter-process/task communication. EE 898 -HW/SW co-design - 11 -
Splitting of tasks No blocking of resources while waiting for input, more flexibility for scheduling, possibly improved result. EE 898 -HW/SW co-design - 12 -
Merging and splitting of tasks The most appropriate task graph granularity depends upon the context merging and splitting may be required. Merging and splitting of tasks should be done automatically, depending upon the context. EE 898 -HW/SW co-design - 13 -
Automated rewriting of the task system - Example * T 2 ** T 2 EE 898 -HW/SW co-design - 14 -
Attributes of a system that needs rewriting Tasks blocking after they have already started running EE 898 -HW/SW co-design - 15 -
High-level optimization: Floating-point to fixed point conversion • Pros – Lower cost – Faster (75%) – Lower power consumption (76%? ? ) – Sufficient SQNR, if properly scaled – Suitable for portable applications • Cons – Decreased dynamic range – Finite word-length effect, unless properly scaled • Overflow and excessive quantization noise – Extra programming effort EE 898 -HW/SW co-design © Ki-Il Kum, et al. (Seoul National University): A Floatingpoint To Fixed-point C Converter For Fixedpoint Digital Signal Processors, 2 nd SUIF Workshop, 1996 - 16 -
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