Florence KTH Stockholm Trieste Rome CNR Florence Siegen

Florence KTH, Stockholm Trieste Rome CNR, Florence Siegen Data Acquisition System of the PAMELA Experiment Alessandro Basili INFN Roma II, Università di Roma “Tor Vergata” Naples

Presentation Overview 1) The acquisition strategy: system requirements and constraints data reduction solution trigger-busy mechanism 2) System details: Interface Data Acquisition board (IDAQ) Pamela Storage and Control Unit (PSCU) 3) Related topics: software organization housekeeping

Requirements & constraints Trigger rate estimation: - S 1 x S 2 x S 3 12 Hz / G. F. = 20. 5 cm 2 sr Packet size per event: 6 KBytes (roughly), more then 40, 000 analog channels q 6 downloads per day q 200 seconds connection 6 speed rate of 12 MBps q GByte per day

Data reduction solution Trigger board ü Front end boards Tracker DSP A/D Calorimeter A/D DSP A/D Tof ü DSP boards A/D ü Trigger board ü IDAQ board ü PSCU DSP IDAQ A/D AC A/D DSP A/D ND A/D S 4

Trigger-busy mechanism S 1 q Trigger board sends trigger to every one, only if the idaq busy signal is released. S 2 q Idaq starts in busy condition. q Only at the end of settings configurations will be sent a “release busy” command S 3 busy Power on Idaq Trigger trigger PSCU Trigger delivered Trigger vetoed

PSCU-IDAQ protocol - Trigger mode 1) Settings before the acquisition: - initialization - Command queue selection - calibration 2) DMA arming: - Data timeout and Event timeout fixed - Event header written in the Ram 3) Acquisition runs: cycled reloading of the command queue Important: the cpu time consuming is very low; the acquisition is managed by the IDAQ (no interrupt handling)

Event acquisition overview 1) Pamela starts up: the Idaq is busy PSCU 2) First command is sent: RELEASE BUSY 3) First trigger comes and Idaq goes again in “busy” state. Not busy IDAQ 4) The read commands are hanging on because idaq will release the acknoledge to the PIF only after 3. 5 ms from the trigger 5) All the “read event” commands are sent to all subdetectors 6) Once the whole data are stored in PIF Ram, the “DATA TIMEOUT” interrupt will tell the cpu that the acquisition has finished. FE FE FE

Event acquisition overview Vetoed triggers Idaq trigger Idaq busy cmd strb cmd ack daq strb daq ack 3. 5 ms timeout: for compression algorithm Answers from DSP boards Commands to DSP boards

IDAQ : interface data acquisition DSP controller e checker PM & DM TX Mux ALARM RS 422 1 in - 14 out Async interfaces MAIN controller e multiplexer Status & PWR TTL IN-Buffers RX Mux LVDS TTL 14 in - 1 out TTL FLASH CTRL con Hamming codec FLASH 1 Mx 8 RAM CTRL con Hamming codec SRAM 512 Kx 8 CMD Buffer TTL RS 422 LVDS DAQ Buffer LVDS OUT-Buffers BUSY RESET ADSP 2187 TRIGG LVDS

IDAQ : interface data acquisition Ram controller clk_tx tx end_tx RAMSERCLK rx end_cmd RAMRES cmd_nda MCLK cmd_err RAM_ERR A[17. . 0] D[7. . 0] DEC_CMD SERIAL Interface AR[17. . 0] DR[7. . 0] HAMMING RAM Interface BHE OEN WEN CEN BLE WERN OERN CERN BHER BLER

IDAQ : interface data acquisition Flash controller clk_tx tx end_tx FLASHSERCLK rx end_cmd FLASHRES MCLK cmd_err Hamm_err busy AH [19. . 0] DH [7. . 0] DEC_CMD SERIAL Interface AL [19. . 0] DL [7. . 0] HAMMING FLASH Interface RYBYN_H OEN_H WEN_H CEN_H RESETN_H RYBYN_L OEN_L WEN_L CEN_L RESETN_L

IDAQ : interface data acquisition DSP controller n. IS n. IWR n. IAL n. IRD clk_tx tx end_tx DSPSERCLK rx end_cmd cmd_nda DSPRES MCLK checking dsp_err cmd_err dat_err busy n. IAD [15. . 0] SERIAL Interface DEC_CMD IDMA Interface n. IACK n. RESET n. IRQL 0 n. PWD FL 0 FL 1 FL 2 CLKIN mode [3. . 0] PF 4 PF 6 PF 7

PSCU TC TM HKU 1553 MIL STD CMD DAT TAM CPU PIF PCMCIA BUS Sys BUS W BUS R BUS 32 DC/DC Mem Mod 32

CPU module 1) Processor SPARC 32 V 7 2) SRAM 1 M x 32 EDAC protected 3) Boot PROM 17 Mips @24 MHz JTAG provided

CPU module 4) EEPROM 256 K x 32 EDAC protected 5) MIL-STD 1553 Bus Controller/Remote Terminal Function with 64 K x 16 Ram buffer 6) CRIMEA: glue logic for PCMCIA bus controller, parallel S-90 bus interface

SSMM module 1) Eleven indipendent memory columns 2) Each column is composed by 4 Memory Cubes 3) Each Cube is 8 x 8 MB chip SDRAM 4) Eleven indipendent Current Limiter for Latch-up protection 5) DRAMMA: Asic for DRAM managing 8 modules for data storage, 2 for Reed. Solomon Check Symbols and 1 for local redundancy

PIF module FPGA based interface (ALVARO): 1) CMD DMA management 2) DAQ DMA management 3) MM Parallel W/R bus management 4) TAM DMA management 5) 1 programmable Event Timeout 6) 1 programmable Data Timeout

HKU module House keeping unit: FPGA based interface commands 1) 2 serial links RS 422 2) 24 High voltage commands (26 V) 3) 2 Differential Bi-level commands acquisitions 1) 32 Contact closures 2) 8 Bi-level acquisition 3) 4 Differential Bi-level acquisition 4) 16 Analog double ended acquisition 5) 16 Analog double ended thermistors 6) 2 Serial Digital 16 bits acquisition

Considerations and conclusions Considerations: 1) A lot more about housekeeping 2) Redundancy and SEU & SEL protection 3) Software organization 4) Power system Conclusions: 1) Make it simple 2) Strong debug 3) HOPE IT WORKS!!!