Скачать презентацию Feedback Systems Update Alessandro Drago Super B General Скачать презентацию Feedback Systems Update Alessandro Drago Super B General

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Feedback Systems Update Alessandro Drago Super. B General Meeting Perugia 16 -19 June 2009 Feedback Systems Update Alessandro Drago Super. B General Meeting Perugia 16 -19 June 2009

Why a new design • The fast advances of the electronics components make obsolete Why a new design • The fast advances of the electronics components make obsolete the present feedback systems • Low emittance beams ask for low impact feedback systems How • Previous software/hardware legacy • Only one digital processing unit design for both longitudinal & transverse • Low noise front end receiver • 2 nsec longitudinal & transverse kickers • Reuse of old systems when possible • In particular, reuse of the power amplifiers 2 (~50 k$ for each 250 W unit)

Gproto / i. Gp evolution • After a unique first phase collaboration design, four Gproto / i. Gp evolution • After a unique first phase collaboration design, four slightly different hardware layouts have been designed [KEK, SLAC, DIMTEL + old Gproto] • Dmitry Teylman (DIMTEL Inc. ) is going to start an i. Gp new release with 12 bits ADC: he claims that it will be ready for the begin of next year • The new i. GP will have the same price list [100 k$ + tax - %discount] • Interesting connected option: low noise front end [ 30 k$ + tax - %discount] • DIMTEL does NOT sell the FPGA source code! 3

Focusing on the digital processing unit: to do list for in-house R&D starting from Focusing on the digital processing unit: to do list for in-house R&D starting from Gproto / i. GP experience 1) Analog to digital conversion @ 12 bits 2) Digital to analog conversion @ 16 bits 3) DSP in FPGA to implement FIR filters: gateware and firmware 4) Software: Operator Interface with connections to the systems 5) Final PCB including ADC, DAC, FPGA and interfaces 4

ADC 5 ADC 5

6 6

The dynamic range in DAFNE feedback analog blocks is in the range 78 d. The dynamic range in DAFNE feedback analog blocks is in the range 78 d. B – 88 d. B 7

ADC evaluation board • ADS 5463 EVM • Name. ADS 5463 Evaluation Module. Status. ADC evaluation board • ADS 5463 EVM • Name. ADS 5463 Evaluation Module. Status. ACTIVE • Price (US$) $299. 00 8

DAC • MAX 5891 • 16 -Bit, 600 Msps, High. Dynamic. Performance DAC with DAC • MAX 5891 • 16 -Bit, 600 Msps, High. Dynamic. Performance DAC with LVDS Inputs 9

DAC evaluation board Price: $ 145, 00 10 DAC evaluation board Price: $ 145, 00 10

DAC evaluation board 11 DAC evaluation board 11

Xilinx FPGA: Virtex-II Virtex-5 Virtex-6 12 Xilinx FPGA: Virtex-II Virtex-5 Virtex-6 12

Virtex-5 Evaluation Boards [up to now no Virtex-6 boards] • Virtex-5 LXT/SXT FF 1738 Virtex-5 Evaluation Boards [up to now no Virtex-6 boards] • Virtex-5 LXT/SXT FF 1738 Prototyping – AFX-FF 1738 -500 PLATFORM – Platform with Xilinx FPGA $3100 • Virtex-5 LXT/SXT FF 665 Prototyping – AFX-FF 665 -500 PLATFORM – Platform with Xilinx FPGA $2000 • Xtreme. DSP Development Platform — Virtex-5 FPGA ML 506 Edition with XC 5 V-SX 50 T-FFG 1136 (288 DSP inside) $1195 13

FPGA Evaluation Boards AFX-FF 1738 -500 AFX-FF 665 -500 ML 506 14 FPGA Evaluation Boards AFX-FF 1738 -500 AFX-FF 665 -500 ML 506 14

Gproto (Virtex-II) block diagram External PC 15 Gproto (Virtex-II) block diagram External PC 15

Using ML 506 it is possible to include the pc inside the FPGA 16 Using ML 506 it is possible to include the pc inside the FPGA 16

300$ 800 euro 1100$ 1500 euro 17 300$ 800 euro 1100$ 1500 euro 17

This similar project is financed by CSNV Human interface by a browser 18 This similar project is financed by CSNV Human interface by a browser 18

Another Virtex-4 solution • Agilent U 1083 A 003 • Acqiris RVM 4400 High-Speed Another Virtex-4 solution • Agilent U 1083 A 003 • Acqiris RVM 4400 High-Speed 6 U • VME/VXS ADC/DAC Module • 10 -bit ADC, 14 -bit DAC, 1. 2 GS/s • Price ~24 k euro 19

Conclusion • A new version of i. GP @ 12/16 bits should be ready Conclusion • A new version of i. GP @ 12/16 bits should be ready at the begin of next year by DIMTEL, Inc. [but no FPGA source code] • The in-house upgrade of feedback digital processing unit is underway • Different design solutions are available, but it is necessary to know the amount of bunch-by-bunch feedback budget, when it will start and who will pay (Super. B TDR, NTA, CSNV, others. . . ) 20