ELEC 516 VLSI System Design and Design Automation

ELEC 516 VLSI System Design and Design Automation Spring 2010 Course Description Chi-ying Tsui Department of Electrical and Electronic Engineering HKUST eetsui@ee. ust. hk Rm: 2522 1 ELEC 516/10 course_des

Outline q About this class q Course Description q About the instructor q Course Content: Lectures, Labs and Textbook q Course Grading q Web site: URL: http: //www. ee. ust. hk/~elec 516 2 ELEC 516/10 course_des

About the class q Prerequisite: ELEC 152, ELEC 301, – Basic knowledge on Digital design, and CMOS VLSI Design q Teaching Team – Instructor: Prof. Chi-Ying Tsui X 7071, Rm. 2520 • Email: eetsui@ece. ust. hk – TA: Qian Zhi. Liang X 8844, Rm. 3114, qianzl@ece. ust. hk q Class time: Tuesday 3: 00 p. m. to 5: 50 p. m. q Office Hour: Tuesday 1: 00 p. m. to 3: 00 p. m. – Lab: Free access all time to room 3114(A). 3 ELEC 516/10 course_des

Background of the course q In ELEC 301 we have learned: – The basics of VLSI design, – Analysis of digital circuits (Static and dynamic performance) – How to optimize the performance of simple and complex gates q As the technology is scaling down, more and more devices are being implemented on a single chip leading to: – More complex systems on a chip – Challenging design task as millions/billions of transistors are integrated. q Design automation and new design methodologies are therefore required to assist the Engineers in complex tasks 4 ELEC 516/10 course_des

Course Description 5 q ELEC 516 is dedicated for advanced Digital VLSI design technique for high performance and low power. – Design complex system such as System-on-chip (SOC) design flow q Design methodology such as top-down synthesis approach, design for testing will be discussed. q Design of digital arithmetic blocks will be covered. q Other building blocks, such as memory will covered q Other design issues such as clocking, interconnect, power delivery, testing will also be covered q Low Power Design techniques will be covered q Specialized Application specific VLSI Architectures will be discussed if time permits. q Extensive use of CAD tools and HDL modeling - Synopsys and Cadence Tools q Design project ELEC 516/10 course_des

Philosophy q Beside theoretical aspect of the course, it is a very practical one which would give you a first hand experience on advanced digital design techniques. q Lectures will allow you to understand all the design aspects and analysis of complex digital CMOS circuits. q Tutorials will cover VHDL, use of CAD Tools and Design Flow q Projects and HW will cover practical aspects of the course by designing circuits for real-life applications. q Even though detailed lectures are provided, you are encouraged to go through the textbook. q Lectures will cover the most important aspects, show different approaches and methodologies of CMOS design. q Projects in Cadence and Synopsys (Industry standard software). 6 ELEC 516/10 course_des

Philosophy q The goal is that everybody learns “something” and would be able to design, complex digital system using automated tools. The goal is also to learn advanced design techniques for digital systems. q “Something” also depends on your motivations and interest. q Open door policy is provided by the instructor: Don’t hesitate to ask questions and to consult with the instructor during the provided consultation hours q If you don’t understand any point don’t hesitate to ask and do not leave it until it’s too late. q Do not hesitate to discuss your difficulties with the instructor. 7 ELEC 516/10 course_des

About the Instructor: Dr. Chi Ying Tsui, Office: EEE, Room 2520 Phone: 2358. 7071, Email: eetsui@ee. ust. hk q Master and Ph. D in Computer Engineering from University of Southern California, USA. q ECAD algorithm design and VLSI Design Flow q Low Power and High performance VLSI implementation of digital systems such as wireless system baseband multimedia applications. q VLSI design of Power Management System for portable applications q Network-on-chip implementation. q Embedded System design for multimedia applications q Energy Harvesting Systems 8 ELEC 516/10 course_des

Text and Reference Books q Major Text: – J. Rabaey, A. Chardrakasan, B. Nikolic, “Digital Integrated Circuits - A Design Perspective”, 2 nd Edition, Prentice Hall – "VHDL: Analysis and Modeling of Digital Systems", by Zainalabedin Navabi, 2 nd Edition q Major Reference: – Weste and Eshraghian “Principles of CMOS VLSI Design - A System Approach” Third Edition – Wayne Wolf, “Modern VLSI Design, System-on-chip Design”, third edition – "Synthesis and Optimization of Digital Circuits", by Giovanni De Micheli – "A Designer's Guide to VHDL Synthesis" by Douglas E. Ott and Thomas J. Wilderotter – Synopsys Manual – Cadence Design Systems documentation – Research papers 9 ELEC 516/10 course_des

Lecture Outlines -Addition tutorial on VHDL and synthesis on the second to the fifth week. 10 ELEC 516/10 course_des

Assignments q 3 -4 Assignments q 1 st and 2 nd on VHDL and synthesis flow – Objective – to get familiar with VHDL and the tools q 3 rd and 4 th Assignments – problem solving questions 11 ELEC 516/10 course_des

Course Grading q Examinations : 60% – Mid-term Examination: 20% – Final Examination: 40% q Assignment: 15% – There are two types of homeworks • Lab type of homework - you have to use CAD tools to do the homework, you have to hand in specific reports for these type of homework. For some homework, you may need to arrange a time demonstrate your result to the TA. • Written homework – problem solving homework q Course projects : (25%) 12 ELEC 516/10 course_des

Design Project q Group project: Personal per group ~ 2 – Team work is important q Designing a chip from specification down to layout q Tasks to be finished – Specification: High-level model – Logic Design: Synthesis and simulation – Layout Design of critical block – Verification - simulation for different abstraction level – Final Layout of the chip – Performance estimation of the chip q Grading will be based on correctness, area, performance and power of the design q Project Title will be given at week 7. q Project group formation by week 8. q Project Demo and Design report –week 15 q Workload: The work of the project should be done jointly. You are responsible for time arrangement, workload and distribution of the task. You are required to sign a declaration indicating the relative amount of work (in %) each member of the group has contributed. 13 ELEC 516/10 course_des

Assumed Background knowledge q Basic CMOS circuit theory and design technique – resistance, capacitance, inductance – MOS gate characteristics – Different CMOS logic design technique – Basic performance evaluation q Use of modern EDA tools – simulation, validation (HSPICE) – schematic capture tools (Cadence) q Logic design – logical minimization, FSMs, component design 14 ELEC 516/10 course_des