EEL-3705 Digital Logic Design Spring 2006 Semester Professor

EEL-3705 Digital Logic Design Spring 2006 Semester Professor R. J. Perry

Announcements FSU First-Day Mandatory Attendance Policy FAMU First-Week Mandatory Attendance Policy ECE Course Prerequisite Policy ECE Academic Dishonesty Policy Today’s Agenda

Today’s Agenda n n n n n Sign-in sheet EEL-3705 Course Outline and Objectives ECE Prerequisite Policy Form HW#1 EEL-3705 Best Practices EEL-3705 Software Distribution Design Methodology Design Abstraction EEL-3705 Design Example Chapter 1– Number Systems

Course Outline and Objectives

Course Notes All slides will be available online Exam, HW, and Quiz solutions online

HW#1 Due 1/18/2006 Individual assignment If needed, enroll in course webpage Review Course Outline Read Chapter 0 Complete Online Quiz #1 Download HW grading sheet “Digitally Drop” Word Document n Include your Name, Home University, Email Address, Intended major, and a brief essay (less than one page) on “Why you want to be an electrical or computer engineer? ” Send email to course instructor after dropping assignment Submit grading sheet on 1/18/2006

Homework Assignments Two weeks to complete an assignment n No excuse for: network down, printer out of toner, computer locks up, etc. HW assignments will “overlap” n Average one assignment due every 1 ½ weeks. HW’s will build upon one another n You may use solutions from previous HW’s Homework assignments will be customized n n Solutions will be given for a “general” problem Individual online quizzes with most assignments You must have working design for full credit

Homework Assignments HW’s are “self-correcting” for the “right answer. ” n I’ll check for the “correct” solution. HW must be on time n n n Digital Drop Box (time stamped) Both you and your partner must digitally submit. Only one copy of handwritten notes needed per group. Only one HW grading sheet needed per group. HW is due at the BEGINNING of class!!!!!

EEL-3705 HW#2 Due: 1/25/2006 Reading Assignment: n Chapter 1 except for section 1. 2. 2 Online Assignment: Quizzes #2 n n Quiz A: Bin 2 Dec and Dec 2 Bin conversions Quiz B: Two’s complement calculations Quiz C: Binary addition Quiz D: Binary subtraction Book/Take-home Assignment: none Quartus II Assignment: none Comments: n Use % in front of binary results on online quizzes

Design Projects Design projects DO NOT replace regular homework assignments. n You may have both due during the same week. Hardware MUST work for more than ½ credit

TPS Quizzes In-class quizzes. Designed to “keep you awake. ” Mostly group quizzes No make-up quizzes will be given n n Used to monitor attendance I will drop the three lowest quiz grades

Definition: System Design Process Requirements Specification Conceptualization Analysis Iteration Synthesis Verification Documentation

EEL-3705: System Design Process Requirements Specification n Given by me: HW, Project, Exam, etc. Conceptualization n Developed by you and your group Iteration Design Cycle Design Logic Circuit Draw Logic Circuit Debug Circuit Errors Examine output results Debug Logical Errors Examine hardware results* Debug Hardware Errors* Iteration

EEL-3705: System Design Process Documentation n “Digitally dropped” into Blackboard Site This could take one hour or thirty hours depending on your skills. I will help you avoid “landmines”

EEL-3705 Best Practices Or, How do you get an A in this class?

Collaborative Learning methodology in which students are not only responsible for their own learning but for the learning of other members of the group.

EEL-3705 Best Practices Keep up with the course!!! n Coming to class. HW is 5% which is equal to ½ a letter grade For example, w/o HW, you need 90 of 95 points (or 95%) for an A n n Reading assignments. HW assignments. Quizzes Project assignments Complete the Assignments!!! n You will be allowed to work in groups, but

EEL-3705 Best Practices The only way to learn to design logic circuits is to design logic circuits.

EEL-3705 Best Practices In other words, practice makes perfect.

EEL-3705 Best Practices Or, you will NOT learn how to design by watching me design

EEL-3705 Software Distribution

Quartus 5. 0 Web Edition MS Windows Digital Logic Design Software n n Schematic Capture Editor Complier Design Simulator Hardware Downloader Available on COE network Download link available on Blackboard site

Design Methodology

Definition: Engineering Design Methodology A systematic approach to achieve the desired goal of a solution to the problem (i. e. working design) using proven principles or practices. Must follow EEL-3705 “Best Practices” design methodology for full credit on assignments

Design Methodology “Right Answers” Violates “Best Practices” “Right answer” but not correct solution. “Best Practices Solution”

Design Abstraction How do we “describe” a system?

Design Abstraction Example: Design a “system” which will complement input A A F(x) Y=A A and Y are single bit values We can “describe” this design using a logical Truth Table A Y 0 1 1 0

Levels of Design Abstraction Our goal in ECE is physical or hardware implementations of the design. In ECE, we “design” at several levels of “abstraction”

Levels of Design Abstraction System: Assembly Language Behavioral: VHDL Logical: Gates Electronic Circuit: Transistors Integrated Circuit: IC Layout Fabrication: IC Processing

Levels of Design Abstraction Example: Design a “system” which will complement input A System Level: EEL-4746 (M 68 HC 11) A ASM Code Y=A M 68 HC 11 Assembly Language COMA STAA Y

Levels of Design Abstraction Example: Design a “system” which will complement input A Behavioral Level: EEL-4712 A Not A VHDL Y <= not A; Y=A

Levels of Design Abstraction Example: Design a “system” which will complement input A Gate Level: EEL-3705 Digital Logic Design A Y=A Inverter or NOT gate

Levels of Design Abstraction Example: Design a “system” which will complement input A Circuit Level: EEL-3300 Electronics I PFET Y=A A NFET CMOS Technology

Levels of Design Abstraction Example: Design a “system” which will complement input A Digital IC Design: EEL-4313 Digital IC Design Y=A VDD GND A CMOS Technology

Levels of Design Abstraction Fabrication Level: EEL-4330 Microelectronics Eng

Summary of Levels System: Assembly Language Behavioral: VHDL Logical: Gates Electronic Circuit: Transistors Integrated Circuit: IC Layout Fabrication: IC Processing

Summary All “levels” give you the same result. We will learn how to use the “logical” or gate level to its most effectiveness this semester.

EEL-3705 Digital Logic Design

Microprocessor-Based System To I/O Microprocessor e. g. Pentium 4 Write software to control the system!!!!

Digital Logic Based System Design the “Digital Logic Core” to control the system!!!!!!

Design Example

Example 2– 2 -bit Up Counter State Diagram Clock is implied

Example – 2 -bit Up Counter State Table ps S 0 S 1 S 2 S 3 ns S 1 S 2 S 3 S 0 State Value Assignment y 0 1 2 3 Let S 0 = reset state Let S 0 = 00 S 1 = 01 S 2 = 10 S 3 = 11 Output Vector

Example – 2 -bit Up Counter Truth Table ps 1 ps 0 ns 1 ns 0 0 1 0 1 0 1 1 0 0 y 1 0 0 1 1 y 0 0 1

Example – 2 -bit Up Counter Excitation Equations

Moore Finite State Machine Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Logic Diagram Block Reg F Logic Y Vector H Logic No X Vector in this Example No H Logic needed

Logic Diagram

Course Project

Temperature Sensors Course Project n Design a simple temperature sensor using digital logic ADC = 8 -bit Analog to Digital Converter Converts an analog signal into a digital signal Temp Sensor = Temp to voltage transducer (analog) Your design = “talks” to the ADC Display = LED based seven-segment display