EE 319 K Introduction to Embedded Systems Lecture 7: Phase-locked-loop, Data structures, Finite state machines, Interrupts https: //www. youtube. com/playlist? list=PLyg 2 vm. Iz. Gx. XEle 4_R 2 VA_J 5 uw. TWktd. WTu Read Sections 4. 3, 6. 5, 9. 1, and 9. 2 Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -1
Agenda q Recap v. Indexed Addressing and Pointers o In C: Address of (&), Pointer to (*) v. Data Structures: Arrays, Strings o Length: hardcoded vs. embedded vs. sentinel o Array access: indexed vs. pointer arithmetic v. Functional Debugging v. Sys. Tick Timer q Outline Called by TExa. S_Init v. Phase Lock Loop (PLL) v. Use struct to create Data structures v. Finite State Machines, Linked data structures v. Interrupts Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -2
Recap: Array access (assembly) q Calculate address from Base and index v. Byte v. Halfword v. Word v. Size_N Base+index Base+2*index Base+4*index Base+N*index q Access sequentially using pointers v. Byte v. Halfword v. Word v. Size_N pt = pt+1 pt = pt+2 pt = pt+4 pt = pt+N Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -3
Recap: Array access (C) q Calculate address from Base and index v. Byte v. Halfword v. Word v. Size_N array_name[index] q Access sequentially using pointers v. Byte v. Halfword v. Word v. Size_N pt = pt+1; *pt Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -4
Phase-Lock-Loop What? Why? How? q Internal oscillator requires minimal power but is imprecise q External crystal provides stable bus clock q TM 4 C 123 is equipped with 16 MHz crystal and bus clock can be set to a maximum of 80 MHz Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -5
Abstraction q Software abstraction v Define a problem with a minimal set of basic, abstract principles / concepts v Separation of concerns via interface/policy mechanisms v Straightforward, mechanical path to implementation q Three advantages of abstraction are 1. it can be faster to develop 2. it is easier to debug (prove correct) and 3. it is easier to change Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -6
Finite State Machine (FSM) q Finite State Machines (FSMs) v. Set of inputs, outputs, states and transitions v. State graph defines input/output relationship q What is a state? v. Description of current conditions q What is a state graph? v. Graphical interconnection between states q What is a controller? v. Software that inputs, outputs, changes state v. Accesses the state graph https: //www. youtube. com/playlist? list=PLyg 2 vm. Iz. Gx. XEle 4_R 2 VA_J 5 uw. TWktd. WTu Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -7
Finite State Machine (FSM) q What is a finite state machine? v. Inputs (sensors) v. Outputs (actuators) v. Controller v. State graph Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -8
Finite State Machine (FSM) q Moore FSM voutput value depends only on the current state, vinputs affect the state transitions vsignificance is being in a state q Input: when to change state q Output: definition of being in that state Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -9
Finite State Machine (FSM) q Moore FSM Execution Sequence 1. Perform output corresponding to the current state 2. Wait a prescribed amount of time (optional) 3. Read inputs 4. Change state, which depends on the input and the current state 5. Go back to 1. and repeat We will not do Mealy FSMs in EE 319 K Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -10
Finite State Machine (FSM) Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -11
FSM Implementation q Data Structure embodies the FSM vmultiple identically-structured nodes vstatically-allocated fixed-size linked structures vone-to-one mapping FSM state graph and linked structure vone structure for each state q Linked Structure vpointer (or link) to other nodes (define next states) q Table structure vindices to other nodes (define next states) Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -12
Traffic Light Control PE 1=0, PE 0=0 means no cars exist on either road PE 1=0, PE 0=1 means there are cars on the East road PE 1=1, PE 0=0 means there are cars on the North road PE 1=1, PE 0=1 means there are cars on both roads go. N, wait. N, go. E, wait. E, PB 5 -0 = 100001 makes it green on North and red on East PB 5 -0 = 100010 makes it yellow on North and red on East PB 5 -0 = 001100 makes it red on North and green on East PB 5 -0 = 010100 makes it red on North and yellow on East http: //users. ece. utexas. edu/~valvano/arm/C 10_Table. Traffic. Light. zip Bard, Gerstlauer, Valvano, Yerraballi 7 -13
Traffic Light Control http: //youtu. be/kg. ABPjf 9 q. LI Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -14
Linked Data Structure OUT WAIT NEXT go. N EQU EQU DCD DCD wait. N DCD DCD go. E DCD DCD wait. E DCD DCD 0 ; offset for output 4 ; offset for time (10 ms) 8 ; offset for next 0 x 21 ; North green, East red 3000 ; 30 sec go. N, wait. N, go. N, wait. N 0 x 22 ; North yellow, East red 500 ; 5 sec go. E, go. E 0 x 0 C ; North red, East green 3000 ; 30 sec go. E, wait. E 0 x 14 ; North red, East yellow 500 ; 5 sec go. N, go. N Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi In ROM 7 -15
FSM Engine (Moore) ; Port and timer initialization LDR R 4, =go. N ; state pointer LDR R 5, =SENSOR ; Port. E LDR R 6, =LIGHT ; Port. B FSM LDR R 0, [R 4, #OUT] ; 1. output value STR R 0, [R 6] ; set lights LDR R 0, [R 4, #WAIT] ; 2. time delay BL Sys. Tick_Wait 10 ms LDR R 0, [R 5] ; 3. read input LSL R 0, #2 ; offset(index): ; 4 bytes/address ADD R 0, #NEXT ; 8, 12, 16, 20 LDR R 4, [R 4, R 0] ; 4. go to next state B FSM Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -16
FSM Data Structure in C (Indexes) const struct State { uint 32_t Out; uint 32_t Time; // 10 ms units uint 32_t Next[4]; // list of next states }; typedef const struct State STyp; #define go. N 0 #define wait. N 1 #define go. E 2 #define wait. E 3 STyp FSM[4] = { {0 x 21, 3000, {go. N, wait. N, go. N, wait. N}}, {0 x 22, 500, {go. E, go. E}}, {0 x 0 C, 3000, {go. E, wait. E}}, {0 x 14, 500, {go. N, go. N}} }; 7 -17
FSM Engine in C (Indexes) void main(void) { uint 32 CS; // index of current state uint 32_t Input; // initialize ports and timer … CS = go. N; // start state while(1) { LIGHT = FSM[CS]. Out; // set lights Sys. Tick_Wait 10 ms(FSM[CS]. Time); Input = SENSOR; // read sensors CS = FSM[CS]. Next[Input]; } } 7 -18
FSM Data Structure in C (Pointers) const struct State { uint 32_t Out; uint 32_t Time; // 10 ms units const struct State *Next[4]; }; typedef const struct State STyp; #define go. N &FSM[0] #define wait. N &FSM[1] #define go. E &FSM[2] #define wait. E &FSM[3] STyp FSM[4] = { {0 x 21, 3000, {go. N, wait. N, go. N, wait. N}}, {0 x 22, 500, {go. E, go. E}}, {0 x 0 C, 3000, {go. E, wait. E}}, {0 x 14, 500, {go. N, go. N}} }; Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -19
FSM Engine in C (Pointers) void main(void) { STyp *Pt; // state pointer uint 32_t Input; // initialize ports and timer … Pt = go. N; // start state while(1) { LIGHT = Pt->Out; // set lights Sys. Tick_Wait 10 ms(Pt->Time); Input = SENSOR; // read sensors Pt = Pt->Next[Input]; } } Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -20
Thought Exercise: Implement Lab 3 as an FSM q 2) The system starts with the LED on q 3) Wait about 62 ms q 4) If the switch is pressed , then toggle the LED once, else turn the LED on. q 5) Steps 3 and 4 are repeated over and over Bard, Gerstlauer, Valvano, Yerraballi 7 -21
State Transition Table Num Name 6 -LED PF 3 -1 Time In=0 In=1 In=2 In=3 In=4 In=5 In=6 In=7 0 Go. W West Red green 1 West Red yellow 2 South Red green 3 South Red yellow 4 Both Green red 5 Both Red red 6 All red off Bard, Gerstlauer, Valvano, Yerraballi Add more rows 7 -22
Interrupts q An interrupt is the automatic transfer of software execution in response to a hardware event (trigger) that is asynchronous with current software execution. vexternal I/O device (like a keyboard or printer) or van internal event (like an op code fault, or a periodic timer. ) q Occurs when the hardware needs or can service (busy to done state transition) Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -23
Interrupt Processing Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -24
ARM Cortex-M Interrupts q Each potential interrupt source has a separate arm bit v Set for those devices from which it wishes to accept interrupts, v Deactivate in those devices from which interrupts are not allowed q Each potential interrupt source has a separate flag bit v hardware sets the flag when it wishes to request an interrupt v software clears the flag in ISR to signify it is processing the request q Interrupt enable conditions in processor v Global interrupt enable bit, I, in PRIMASK register v Priority level, BASEPRI, of allowed interrupts (0 = all) Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -25
Interrupt Conditions q Four conditions must be true simultaneously for an interrupt to occur: 1. 2. 3. 4. Arm: control bit for each possible source is set Enable: interrupts globally enabled (I=0 in PRIMASK) Level: interrupt level must be less than BASEPRI Trigger: hardware action sets source-specific flag q Interrupt remains pending if trigger is set but any other condition is not true v Interrupt serviced once all conditions become true q Need to acknowledge interrupt v Clear trigger flag or will get endless interrupts! Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -26
Interrupt Processing 1. The execution of the main program is suspended 1. the current instruction is finished, 2. suspend execution and push 8 registers (R 0 -R 3, R 12, LR, PC, PSR) on the stack 3. LR set to 0 x. FFFFFFF 9 (indicates interrupt return) 4. IPSR set to interrupt number 5. sets PC to ISR address 2. The interrupt service routine (ISR) is executed v clears the flag that requested the interrupt v performs necessary operations v communicates using global variables 3. The main program is resumed when ISR executes BX LR v pulls the 8 registers from the stack Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -27
Registers R 0 -R 3 parameters R 4 -R 11 must be saved R 14, R 15 are important SP (R 13) refers to PSP or MSP We will use just the MSP PRIMASK has intr. enable (I) bit BASEPRI has allowed intr. priority Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -28
Priority Mask Register Disable interrupts (I=1) CPSID I Enable interrupts (I=0) CPSIE I MRS R 0, PRIMASK CPSID I MRS PRIMASK, R 0 Interface latency Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -29
Program Status Register q Accessed separately or all at once Q = Saturation, T = Thumb bit Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -30
Interrupt Program Status Register (ISPR) Run debugger: - stop in ISR and - look at IPSR Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -31
Interrupt Context Switch Vector address for GPIO Port C Interrupt Number 18 corresponds to GPIO Port C Bard, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi 7 -32
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