ECE 424 Design of Microprocessor-Based Systems Intel 8088

ECE 424 Design of Microprocessor-Based Systems Intel 8088 (8086) Microprocessor Structure Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology Microprocessor System Design 1

Overview q Textbook: J. L. Antonakos, "An Introduction to the Intel Family of Microprocessors, " Third Edition, Prentice Hall, 1999 q Objectives: The course will provide knowledge to build and program microprocessor-based systems. § Microprocessor architecture § Architecture of microprocessor-based systems § Programming microprocessor-based systems § Future trends q Grading: Two midterms, one final exam, and homeworks Microprocessor System Design 2

What are microprocessor-based systems? q Microprocessor-based systems are electrical systems consisting of microprocessors, memories, I/O units, and other peripherals. Microprocessors are the brains of the systems Microprocessors access memories and other units through buses The operations of microprocessors are controlled by instructions stored in memories Microprocessor Bus Control unit Datapath ALU Reg. Memory Output units Microprocessor System Design Input units 3

What are microprocessors? q A microprocessor is a processor (or Central Processing Unit, CPU) fabricated on a single integrated circuit. Address bus MAR PC IR Control unit Control bus X Data bus Y ALU ACC A simple microprocessor architecture Microprocessor System Design 4

Evolution of Computers q First generation (1939 -1954) - vacuum tube q Second generation (1954 -1959) - transistor q Third generation (1959 -1971) - IC q Fourth generation (1971 -present) - microprocessor Microprocessor System Design 5

Evolution of Computers q First generation (1939 -1954) - vacuum tube IBM 650, 1954 Http: //history. acusd. edu/gen/recording/computer 1. html http: //www. cs. virginia. edu/brochure/museum. html http: //www. columbia. edu/acis/history/650. html Microprocessor System Design 6

Evolution of Computers q Second generation (1954 -1959) - transistor Manchester University Experimental Transistor Computer Http: //history. acusd. edu/gen/recording/computer 1. html http: //www. computer 50. org/kgill/transistor/trans. html Microprocessor System Design 7

Evolution of Computers q Third generation (1959 -1971) - IC PDP-8, Digital Equipment Corporation Thanks to the use of ICs, the DEC PDP-8 is the least expensive general purpose small computer in 1960 s Http: //history. acusd. edu/gen/recording/computer 1. html http: //www. piercefuller. com/collect/pdp 8. html Microprocessor System Design 8

Evolution of Computers q Fourth generation (1971 -present) - microprocessor In 1971, Intel developed 4 -bit 4004 chip for calculator applications. ROM/RAM buffer Timing Reset Control logic Program counter Instruction decoder ALU Reg. I/O Refresh logic http: //www. intel. com System bus Block diagram of Intel 4004 chip layout A good review article: The History of The Microprocessor, Bell Labs Technical Journal, Autumn, Microprocessor System Design 1997 9

Evolution of Intel Microprocessors Minimum transistor sizes (µm) Number of transistors P III Pentium 80386 8088 80486 P 4 8080 P II 80286 8088 8080 80386 Pentium P III P 4 80486 80286 Clock frequencies (MHz) MIPS P 4 P III Pentium P III 80386 8088 8080 80386 80486 80286 8080 8088 Microprocessor System Design P 4 P II 80486 80286 10

Other Commercial Microprocessors q Power. PC (IBM, Motorola) q Athlon, Dulon, Hammer (AMD) q Crusoe (Transmeta) q SPARC, Ultra. SPARC (Sun Microsystems) q TI’s TMS DSP chips (Texas Instruments) q Star. Core (Motorola, Agere) q ARM cores (Advanced RISC Machines) q MIPS cores (MIPS Technologies) q Microprocessor System Design 11

Applications of Microprocessor-Based Systems q Computers System performance is normally the most important design concern . . . Keyboard Monitor Disk Other peripherals Bus Microprocessor Memory Timing & control . . . Interrupt control Block diagram of a computer Microprocessor System Design 12

1. 3 System block diagram • Crystal oscillator • Timing circuitry (counters dividing to lower frequencies) Timing • ROM (Read Only Memory) (start-up program) • RAM (Random Access Memory) • Bus controller P + • DRAM (Dynamic RAM) associated • Bus drivers high capacity, refresh needed logic • SRAM (Static RAM) - low • Coprocessor circuitry: power, fast, easy to interface CPU Memory System bus (data, address & control signals) Parallel I/O Many wires, fast. • Printer (high resolution) • External memory • Floppy Disk • Hard Disk • Compact Disk • Other high speed devices Serial I/O Interrupt circuitry Simple (only two wires + ground) but slow. At external unexpected events, P has to interrupt the main program execution, service the interrupt request (obviously a short subroutine) and retake the main program from the 13 point where it was interrupt. • Printer (low resolution) • Modem • Operator’s console • Mainframe • Personal computer

The Personal Computer Speaker Timer logic (8253) Processor (8086 trough Pentium Coprocessor (8087 trough 80387 System ROM 640 KB DRAM System bus (data, address & control signals) Keyboard logic (8253) Keyboard DMA Controller (8237) Expansion logic Video card Disk controller Serial port. . . Interrupt logic (8259) 14 Extension slots

Applications of Microprocessor-Based Systems q Microcontrollers A microcontroller is a simple computer implemented in a single VLSI chip. In general, microcontrollers are cheap and have low performance Microcontrollers are widely used in industrial control, automobile and home applications OSC. RAM ROM CPU I/O port Timer USART Interrupt A/D, D/A Block diagram of a microcontroller Microprocessor System Design 15

Applications of Microprocessor-Based Systems q ASICs http: //www. ti. com Microprocessors are embedded into ASIC chips to implement complex functions In general, it requires that the microprocessors have low power consumption and take small silicon area A TI baseband chip for cellular phone applications Microprocessor System Design 16

Class Objectives q Hardware architecture of microprocessor-based systems Microprocessor architecture Memory organization I/O units of microprocessor-based systems How to put them together q Programming of microprocessor-based systems Intel 80 x 86 instruction set Microprocessor Interrupt services Assembly language programming Microprocessor System Design 17

Overview & Review Microprocessor System Design 18

Overview q Intel 8088 facts Ø 20 bit address bus allow accessing VDD (5 V) 1 M memory locations Ø 16 -bit internal data bus and 8 -bit external data bus. Thus, it need two read (or write) operations to read (or write) a 16 -bit datum 8088 control signals To 8088 Ø Byte addressable and byte-swapping 20 -bit address 8 -bit data control signals from 8088 Word: 5 A 2 F CLK 18001 5 A High byte of word 18000 2 F Low byte of word GND 8088 signal classification Memory locations Microprocessor System Design 19

Organization of 8088 Address bus (20 bits) AH BH Execution Unit (EU) AL BL CH CL DH DL General purpose register SP Segment register BP SI DI Data bus (16 bits) DS SS ALU Data bus (16 bits) ALU Flag register CS ES IP Instruction Queue Bus control External bus EU control Bus Interface Unit (BIU) Microprocessor System Design 20

General Purpose Registers 15 8 7 0 AX AL BX BH BL Base CX CH CL Counter DX Data Group AH Accumulator DH DL Data SP Pointer and Index Group Stack Pointer BP Base Pointer SI Source Index DI Destination Index Microprocessor System Design 21

Arithmetic Logic Unit (ALU) A B n bits F n bits Carry Y= 0 ? F A>B? 0 0 1 1 0 0 Y 0 1 0 1 A+B A -1 A and B A or B not A Y Ø Signal F control which function will be conducted by ALU. Ø Signal F is generated according to the current instruction. Ø Basic arithmetic operations: addition, subtraction, Ø Basic logic operations: and, or, xor, shifting, Microprocessor System Design 22

Flag Register q Flag register contains information reflecting the current status of a microprocessor. It also contains information which controls the operation of the microprocessor. 15 0 OF DF IF TF SF ZF AF PF CF Ø Status Flags Ø Control Flags IF: DF: TF: Interrupt enable flag Direction flag Trap flag CF: PF: AF: ZF: SF: OF: Microprocessor System Design Carry flag Parity flag Auxiliary carry flag Zero flag Sign flag Overflow flag 23

Instruction Machine Codes q Instruction machine codes are binary numbers Ø For Example: 100011000011 MOV AL, BL Register mode q Machine code structure Opcode Mode Operand 1 Operand 2 Ø Some instructions do not have operands, or have only one operand Ø Opcode tells what operation is to be performed. (EU control logic generates ALU control signals according to Opcode) Ø Mode indicates the type of a instruction: Register type, or Memory type Ø Operands tell what data should be used in the operation. Operands can be addresses telling where to get data (or where to store results) Microprocessor System Design 24

EU Operation 1. Fetch an instruction from instruction queue 2. According to the instruction, EU control logic generates control signals. (This process is also referred to as instruction AH BH CH DH SP BP SI DI decoding) 3. Depending on the control signal, EU performs one of the following operations: Ø An arithmetic operation Ø A logic operation Ø Storing a datum into a register Ø Moving a datum from a register Ø Changing flag register AL BL CL DL ALU Flag register Microprocessor System Design General purpose register ALU Data bus (16 bits) EU control instruction 10110001010 25

Generating Memory Addresses q How can a 16 -bit microprocessor generate 20 -bit memory addresses? Left shift 4 bits 16 -bit register + FFFFF 0000 16 -bit register Addr 1 + 0 FFFF Offset Addr 1 20 -bit memory address Offset Segment (64 K) Segment address 00000 Intel 80 x 86 memory address generation Microprocessor System Design 1 M memory space 26

Memory Segmentation q A segment is a 64 KB block of memory starting from any 16 -byte boundary Ø For example: 00000, 00010, 00020, 20000, 8 CE 90, and E 0840 are all valid segment addresses Ø The requirement of starting from 16 -byte boundary is due to the 4 -bit left shifting q Segment registers in BIU 15 0 CS Code Segment DS Data Segment SS Stack Segment ES Extra Segment Microprocessor System Design 27

Memory Address Calculation q Segment addresses must be stored in segment registers Segment address q Offset is derived from the combination of pointer registers, the Instruction Pointer (IP), and immediate values + 0000 Offset Memory address q Examples 3 4 8 A 0 CS 4 2 1 4 IP + Instruction address 3 8 A B 4 1 2 3 DS 0 0 DI + Data address 1 2 3 5 SS SP + Stack address 5 0 0 F F 0 0 E 0 4 0 2 6 2 2 Microprocessor System Design 28

Fetching Instructions q Where to fetch the next instruction? 8088 CS IP 1234 0012 Memory 12352 MOV AL, 0 12352 q Update IP — After an instruction is fetched, Register IP is updated as follows: IP = IP + Length of the fetched instruction — For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction, the IP is updated to 0014 Microprocessor System Design 29

Accessing Data Memory q There is a number of methods to generate the memory address when accessing data memory. These methods are referred to as Addressing Modes q Examples: — Direct addressing: MOV AL, [0300 H] DS Memory address 1 1 2 3 0 3 2 6 4 0 0 0 (assume DS=1234 H) — Register indirect addressing: MOV AL, [SI] DS Memory address 1 1 2 3 0 3 4 1 0 0 2 6 5 (assume DS=1234 H) 0 Microprocessor System Design (assume SI=0310 H) 30

Reserved Memory Locations q Some memory locations are reserved for special purposes. Programs should not be loaded in these areas FFFFF Ø Locations from FFFF 0 H to FFFFFH are used for system reset code Ø Locations from 00000 H to 003 FFH are used for the interrupt pointer table It has 256 table entries Each table entry is 4 bytes Reset instruction area FFFF 0 Interrupt pointer table 256 4 = 1024 = memory addressing space From 00000 H to 003 FFH Microprocessor System Design 003 FF 00000 31

Interrupts q An interrupt is an event that occurs while the processor is executing a program q The interrupt temporarily suspends execution of the program and switch the processor to executing a special routine (interrupt service routine) q When the execution of interrupt service routine is complete, the processor resumes the execution of the original program q Interrupt classification Hardware Interrupts Caused by activating the processor’s interrupt control signals (NMI, INTR) Software Interrupts Caused by the execution of an INT instruction Caused by an event which is generated by the execution of a program, such as division by zero q 8088 can have 256 interrupts Microprocessor System Design 32

Minimum and Maximum Operation modes q Intel 8088 (8086) has two operation modes: Minimum Mode 8088 generates control signals for memory and I/O operations Maximum Mode It needs 8288 bus controller to generate control signals for memory and I/O operations Some functions are not available It allows the use of 8087 coprocessor; in minimum mode it also provides other functions Compatible with 8085 -based systems Microprocessor System Design 33