DØ Run. IIb Trigger Upgrade: Status Darien Wood for the DØ Trigger Upgrade Group 1
Trigger System Upgrades Detector Level 1 7 MHz CAL Level 2 2. 5 k. Hz L 1 Cal 1 k. Hz L 2 Cal Cal-TRK c/f PS L 1 PS L 2 PS CFT L 1 CTT L 2 CTT SMT L 2 STT L 1 Mu MU FPD MU-TRK L 2 Mu L 1 FPD Lumi Framework New (or replaced) System Enhanced System 2 Global L 2 L 3/DAQ <100 Hz Level 3 D 0 PMG 16 -Nov-2004
L 1 Cal Trigger Status ADC+Digital Filtering SCLD prototype has been used successfully in integration tests. Final board has successfully passed bench tests at Saclay Finished 05/03 Clustering Global Sums & Topological ADF v. 2 layout complete, lining up vendors for preproduction run Production track match card fabricated and assembled, loop test established Orders placed for all remaining TAB and GAB components. Production readiness review was October 7 – now in production 3 D 0 PMG 16 -Nov-2004
L 1 Cal Trigger Status VME/SCL SCLD ADF v 1 v 2 4 TAB GAB D 0 PMG 16 -Nov-2004
L 1 Cal progress since Sep 7: ADF · ADF v. 2 layout completed u u gerber files, layout & assembly instructions completed negotiations with three vendors for fabrication and assembly s s s u 5 1 st closed business 2 nd finally declined order 3 rd (ADCO) in progress goal is to complete 10 pre-production modules in next few weeks D 0 PMG 16 -Nov-2004
L 1 Cal progress since Sep 7: TAB & GAB · Continued firmware work at Nevis u u automated facility bit-by-bit comparison of simulated events simple list of L 1 cal trigger terms implemented in GAB · ECL output receiver test card · Successful production readiness review Oct 7 th at Nevis u u u committee: Bob Hirosky (chair), Iain Bertram, Dan Edmunds, Joel Steinberg recommendation to go ahead with production, using existing PCB’s: no modifications required also examined installation commissioning plans and had many useful technical discussions · Assembly orders are now being processed at Columbia 6 D 0 PMG 16 -Nov-2004
L 1 Cal progress since Sep 7: BLS cables and test stand area · UIC and Fermilab working on constructing a 5% system of transition cables/panels/paddles from existing BLS cables to ADF back planes · Impedance matching studies with prototypes · Mock-up of mechanical system and cable routing 7 D 0 PMG 16 -Nov-2004
Current BLS Cables Layout · How the BLS cables are set. Door 6. 5‘‘ Rack We have decided not to move the cables 8 D 0 PMG 16 -Nov-2004
Mock-up We reproduce the current BLS cable layout for 128 BLS cables to test the design and to optimize the procedure to connect the cables 9 D 0 PMG 16 -Nov-2004
L 1 Cal Commissioning u u 10 TAB data transmission to L 2 and L 3, tests of data unpacking cable tests for inputs patch panels/paddle cards for installation in hand cable layouts defined Upgrade rack(s) · Signal splitters allow digital filter and entire readout chain to be tested with full system prior to installation · Currently: Power, ground Comp uters Ground isolation Clock Movable Counting House Current L 1 cal (10 racks) Framework, L 2, etc. Serial command link Split signals “Sidewalk” · Future: u u u Collect single-tower data to tune MC Test trigger generation with real data Full system will be installed on sidewalk D 0 PMG 16 -Nov-2004
L 1 Cal. Track Trigger Overview 11 D 0 PMG 16 -Nov-2004
Progress since Sep 7: L 1 Cal-track match · Production MTCxx cards fabricated u will be sent for assembly shorty · Layout completed for production UFB: u will be sent for fab in next few days · Collision hall work completed u u termination of long-haul cables completed ready for pre-commissioning after end of shutdown Universal Flavor board (daughter) MTCxx (mother board) 12 D 0 PMG 16 -Nov-2004
L 1 Central Track Trigger · Level 1 Central Track Trigger (CTT) essential for electrons, muons, taus (WH l jj), input for STT vertexing trigger · Tracking trigger rates very sensitive to occupancy · Upgrade stategy: u u Narrow tracker roads by using individual fiber hits (singlets) rather than pairing adjacent fibers (doublets) Cal-track matching DFEA mother/daughter board redesigned as a single board (DFEB), with larger FPGA’s: (Xilinx Virtex-II XC 2 V 6000) 13 D 0 PMG 16 -Nov-2004
Scope of Upgrade L 1 CTT · Original idea was to simply replace FPGAs to newer larger ones that allow more equations · Have recently upscoped the project to allow monitoring and debugging capability · The project now involves replacing two crates of electronics and the crates themselves · All elements in this upgrade have been designed to minimize commissioning time and simplify debugging 14 D 0 PMG 16 -Nov-2004
L 1 CTT progress since Sep 07: DFEA & Crate Controller · Combined DFEA motherboard-daughterboard u u 2 complete boards (at Boston and Fermilab) Boston: test data injection and capture features successfully tested s u Remaining: commission SLDB receiver Fermilab: installed on platform · Crate Controller u u u 15 working well with DFEA on BU test stand eight boards back from B. E. S. T. after BGA and QFN reflow Will be assembled as production boards D 0 PMG 16 -Nov-2004
L 1 CTT progress since Sep 07: crates and platform slice · Fully assembled DFE subrack installed in PW 02 (on platform in collision hall) u u power supplies cables inspection ORC on Oct 26 th (can run unattended) · testing DFEA/M in situ u 16 initializes OK – no problems output fed to 9 th CTOC card testing status bits D 0 PMG 16 -Nov-2004
L 1 CTT parallel chain Mixer LVDS splitters DFEA crates CTOC, etc (current) Extra CTOC, CTTT Fiber signals Trigger framework timing (Serial command link) Partial Prototype crate prototype DFEA controller crate (upgrade) All elements of parallel slice of upgrade prototypes installed in Fall 04 shutdown 17 link PC D 0 PMG 16 -Nov-2004
18 DFEB in new crate installed on the platform in DØ New DFE Crate backplane DFEB in stand-alone test setup with LVDS signals input New L 1 CTT Crate, Crate Controller, DFEB L 1 CTT Hardware D 0 PMG 16 -Nov-2004
STT and Level 2 · STT u u Additional production of the same boards is needed to accommodate new Layer 0 channels Production Readiness Review Friday Sept 10: s s Buffer controller now in production option of building additional Track Fit Cards awaiting final decision · Level 2 u Work in July/August to get the Concurrent Tech c. PCI CPU to work with the 9 u motherboard Fallback CPU: Adlink c. PCI-6860 A u upgrade to proceed adiabatically u Should be “transparent” upgrades 19 D 0 PMG 16 -Nov-2004
Run. IIb Trigger Simulation/Algorithms · L 1 Cal u u u variety of small variations of sliding window algorithm studied for EM triggers now improving upon Run. IIa L 1+L 2 EM performance Prototype firmware versions of EM, Jet, and tau algorithms · L 1 CTT u Run IIa simulation package being restructured s u 20 W->eν MC Single EM will be much more easily adapted to Run IIb Firmware being tested Greg Pawloski, Sabine Lammers D 0 PMG 16 -Nov-2004
Run. IIb Trigger Simulation/Analysis · Primary goal is “strawman” trigger list by early 2005 incorporating new algorithms u starting with current L 2 trigger terms as a basis · “trigger rate tool” adapted to implement sliding windows algorithms u u uses real collider data as input accounts for correlations and combined rates of full trigger list · Closer coordination of effort between u u u 21 Trigger Upgrade Project (coding new algorithms) Trigger Board (policy) Trigger Steering Committee (technical) (new) Trigger Studies Group (physics/rate studies) N. Varelas appointed Trigger Coordinator D 0 PMG 16 -Nov-2004
CTT Manpower · Recommendation from July Director’s review: “Secure the manpower for all installation needs in the 2004 shutdown to allow testing during the data taking in FY 05” u u 22 Additional engineering & technical help obtained for CTT. Additional postdoc for CTT is highest priority D 0 PMG 16 -Nov-2004
Triggers Summary · L 1 cal u u u ADF v. 2 layout finished – 10 boards to be produced continued progress in BLS cable transition TABs and GABs cleared for production in PRR · L 1 caltrack u u production MTCxx heading for assembly production UFB heading for fabrication · L 1 CTT u u · L 2 u u Ongoing tests of DFEA/M, Crate Controller, and backplanes – all look good so far complete parallel chain installed in CH during shutdwon new candidate SBC being evaluated for L 2 beta STT PRR completed, decision about production soon · Simulation u u 23 Cal EM algorithm being finalized, coded More extensive combined simulations with real data D 0 PMG 16 -Nov-2004
Backups 24 D 0 PMG 16 -Nov-2004
Management structure WBS 1. 2: Trigger Upgrade P. Padley (Rice), D. Wood (Northeastern) Project is largely university based WBS 1. 2. 1: Level 1 Calorimeter M. Abolins(MSU), H. Evans(Columbia) WBS 1. 2. 2: Level 1 Cal-track match K. Johns (Arizona) WBS 1. 2. 3: Level 1 Tracking M. Narain (Boston), Don Lincoln (FNAL) WBS 1. 2. 4: Level 2 Beta upgrade R. Hirosky (Virginia) WBS 1. 2. 5: Level 2 STT upgrade U. Heintz (Boston) WBS 1. 2. 6: Trigger Simulation M. Hildreth (ND), E. Barberis (NEU) WBS 1. 2. 7: AFE upgrade (Pending) A. Bross (FNAL) 25 D 0 PMG 16 -Nov-2004
Upgrade L 1 Cal: Major features · Calorimeter trigger upgrade u sharpens turn-on trigger thresholds u more topological cuts · Largest subproject in the trigger upgrade · Will require removing the existing Cal trigger 26 D 0 PMG 16 -Nov-2004
L 1 Cal. Track: Major features · Exploit new L 1 Cal trigger · Improve Run IIa f matching granularity x 8 · Needed in triggers for Higgs searches u u electrons in WH and H W*W modes taus in H tt and H+ t · Fake EM rejection is improved by ~x 2 · Fake t rejection is improved by ~x 10 · Very modest upgrade modeled on existing Mu -Track match system u 27 Very few changes with respect to Mu-Track D 0 PMG 16 -Nov-2004
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